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71. 发明授权

US06343347B1 Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction 失效
标题翻译：具有缓存状态的多处理器系统总线和用于读/转（RCO）地址事务的LRU侦听响应
公开(公告)号：US06343347B1
公开(公告)日：2002-01-29
申请号：US09368224
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0831
摘要： Upon snooping a combined data access and cast out/deallocate operation initiating by a horizontal storage device, snoop logic determines appropriate responses to both the data access and the cast out/deallocate based upon the presence and coherency state of the target of the data access within a corresponding storage device, the presence and coherency state of the victim of the cast out/deallocate within the corresponding storage device, and the presence of an invalid entry within the corresponding storage device in a congruence class including both the target and the victim. The appropriate responses are “merged”, transmitted together in response to the combined operation as either a single response code or discrete response codes within a single response. The coherency state and LRU position of the selected victim for the cast out/deallocate portion of the combined operation may also be appended to the response to facilitate data storage management.
摘要翻译：在窥探组合的数据访问并且由水平存储设备推出/取消分配操作时，窥探逻辑基于数据访问的目标的存在和一致性状态来确定对数据访问和丢弃/释放分配的适当响应，相应的存储设备，对应的存储设备中的丢弃/释放的受害者的存在和一致性状态，以及在包括目标和受害者的一致类中的相应存储设备内的无效条目的存在。适当的响应“合并”，响应于组合操作一起发送，作为单个响应中的单个响应代码或离散响应代码。组合操作的外推/释放部分的所选受害者的相关性状态和LRU位置也可以附加到响应以便于数据存储管理。

72. 发明授权

US07493446B2 System and method for completing full updates to entire cache lines stores with address-only bus operations 有权
标题翻译：使用仅地址总线操作完成对整个高速缓存行存储的完全更新的系统和方法
公开(公告)号：US07493446B2
公开(公告)日：2009-02-17
申请号：US12034769
申请日：2008-02-21
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译：一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。

73. 发明授权

US06779086B2 Symmetric multiprocessor systems with an independent super-coherent cache directory 失效
标题翻译：具有独立超级相干缓存目录的对称多处理器系统
公开(公告)号：US06779086B2
公开(公告)日：2004-08-17
申请号：US09978363
申请日：2001-10-16
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system comprising, in addition to a first and second processor having an respective first and second cache and a main cache directory affiliated with the first processor's cache, a secondary cache directory of the first cache, which contains a subset of cache line addresses from the main cache directory corresponding to cache lines that are in a first or second coherency state, where the second coherency state indicates to the first processor that requests issued from the first processor for a cache line whose address is within the secondary directory should utilize super-coherent data currently available in the first cache and should not be issued on the system interconnect. Additionally, the cache controller logic includes a clear on barrier flag (COBF) associated with the secondary directory, which is set whenever an operation of the first processor is issued to said system interconnect. If a barrier instruction is received by the first processor while the COBF is set, the contents of the secondary directory are immediately flushed and the cache lines are tagged with an invalid state.
摘要翻译：一种多处理器数据处理系统，除了具有相应的第一和第二高速缓存以及隶属于第一处理器的高速缓存的主缓存目录的第一处理器和第二处理器之外，还包括第一高速缓存的副高速缓存目录，其包含高速缓存行的子集来自对应于处于第一或第二相关性状态的高速缓存行的主缓存目录的地址，其中第二一致性状态向第一处理器指示从第一处理器发出的对于地址在次目录内应该利用的高速缓存行的请求超级相干数据目前在第一个缓存中可用，不应在系统互连上发布。此外，高速缓存控制器逻辑包括与副目录相关联的清除屏障标志（COBF），其随着第一处理器的操作被发布到所述系统互连而被设置。如果在设置COBF时由第一处理器接收到屏障指令，则立即刷新副目录的内容，并将高速缓存行标记为无效状态。

74. 发明授权

US06763435B2 Super-coherent multiprocessor system bus protocols 有权
标题翻译：超相干多处理器系统总线协议
公开(公告)号：US06763435B2
公开(公告)日：2004-07-13
申请号：US09978355
申请日：2001-10-16
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
IPC分类号： G06F1314
CPC分类号： G06F12/0831
摘要： A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and responsive to a snoop of the request by the second processor, issuing a first response on the system bus indicating to the requesting processor that the requesting processor may utilize data currently stored within the shared cache line of a cache of the requesting processor. When the request is snooped by the second processor and the second processor decides to release a lock on the cache line to the requesting processor, the second processor issues a second response on the system bus indicating that the first processor should utilize new/coherent data and then the second processor releases the lock to the first processor.
摘要翻译：一种用于提高多处理器数据处理系统的性能的方法，包括：窥探在所述数据处理系统的系统总线上的共享高速缓存行中保存的数据的请求，所述数据处理系统的高速缓存包含所述共享高速缓存行的更新副本，并响应于所述第二处理器的请求，在系统总线上发出第一响应，向请求处理器指示请求处理器可以利用当前存储在请求处理器的高速缓存的共享高速缓存行中的数据。当请求被第二处理器窥探并且第二处理器决定释放到请求处理器的高速缓存行上的锁时，第二处理器在系统总线上发出指示第一处理器应该利用新的/相干数据的第二响应，那么第二处理器将锁定释放到第一处理器。

75. 发明授权

US06658539B2 Super-coherent data mechanisms for shared caches in a multiprocessing system 有权
标题翻译：多处理系统中共享缓存的超连贯数据机制
公开(公告)号：US06658539B2
公开(公告)日：2003-12-02
申请号：US09978353
申请日：2001-10-16
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/084
摘要： A method for improving performance of a multiprocessor data processing system having processor groups with shared caches. When a processor within a processor group that shares a cache snoops a modification to a shared cache line in a cache of another processor that is not within the processor group, the coherency state of the shared cache line within the first cache is set to a first coherency state that indicates that the cache line has been modified by a processor not within the processor group and that the cache line has not yet been updated within the group's cache. When a request for the cache line is later issued by a processor, the request is issued to the system bus or interconnect. If a received response to the request indicates that the processor should utilize super-coherent data, the coherency state of the cache line is set to a processor-specific super coherency state. This state indicates that subsequent requests for the cache line by the first processor should be provided said super-coherent data, while a subsequent request for the cache line by a next processor in the processor group that has not yet issued a request for the cache line on the system bus, may still go to the system bus to request the cache line. The individualized, processor-specific super coherency states are individually set but are usually changed to another coherency state (e.g., Modified or Invalid) as a group.
摘要翻译：一种用于改善具有处理器组与共享高速缓存的多处理器数据处理系统的性能的方法。当共享缓存的处理器组内的处理器窥探在处理器组内的另一处理器的高速缓存中的共享高速缓存线的修改时，第一高速缓存内的共享高速缓存行的一致性状态被设置为第一指示高速缓存行已被处理器组内的处理器修改并且高速缓存行尚未在组的高速缓存内更新的一致性状态。当稍后由处理器发出对高速缓存行的请求时，该请求被发布到系统总线或互连。如果对该请求的接收到的响应指示处理器应该使用超相干数据，则高速缓存行的一致性状态被设置为处理器特定的超一致性状态。该状态指示应该为所述超相干数据提供由第一处理器对高速缓存行的后续请求，而处理器组中尚未发出对高速缓存行请求的下一个处理器对高速缓存行的后续请求在系统总线上，仍然可以去系统总线请求缓存行。个性化的处理器特定的超一致性状态是单独设置的，但是通常作为一组更改为另一个一致性状态（例如，修改或无效）。

76. 发明授权

US06704844B2 Dynamic hardware and software performance optimizations for super-coherent SMP systems 失效
标题翻译：超连贯SMP系统的动态硬件和软件性能优化
公开(公告)号：US06704844B2
公开(公告)日：2004-03-09
申请号：US09978361
申请日：2001-10-16
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
IPC分类号： G06F1210
CPC分类号： G06F12/0831
摘要： A method for increasing performance optimization in a multiprocessor data processing system. A number of predetermined thresholds are provided within a system controller logic and utilized to trigger specific bandwidth utilization responses. Both an address bus and data bus bandwidth utilization are monitored. Responsive to a fall of a percentage of data bus bandwidth utilization below a first predetermined threshold value, the system controller provides a particular response to a request for a cache line at a snooping processor having the cache line, where the response indicates to a requesting processor that the cache line will be provided. Conversely, if the percentage of data bus bandwidth utilization rises above a second predetermined threshold value, the system controller provides a next response to the request that indicates to any requesting processors that the requesting processor should utilize super-coherent data which is currently within its local cache. Similar operation on the address bus permits the system controller to triggering the issuing of Z1 Read requests for modified data in a shared cache line by processors which still have super-coherent data. The method also comprises enabling a load instruction with a plurality of bits that (1) indicates whether a resulting load request may receive super-coherent data and (2) overrides a coherency state indicating utilization of super-coherent data when said plurality of bits indicates that said load request may not utilize said super-coherent data. Specialized store instructions with appended bits and related functionality are also provided.
摘要翻译：一种用于在多处理器数据处理系统中提高性能优化的方法。在系统控制器逻辑中提供多个预定阈值，并用于触发特定带宽利用响应。监视地址总线和数据总线带宽利用率。响应于低于第一预定阈值的百分比的数据总线带宽利用率的下降，系统控制器在具有高速缓存行的窥探处理器处提供对高速缓存行的请求的特定响应，其中响应向请求处理器指示将提供缓存行。相反，如果数据总线带宽利用率的百分比上升到高于第二预定阈值，则系统控制器向请求处理器提供对请求的下一个响应，该请求指示请求处理器应该利用当前在其本地内的超相干数据缓存。地址总线上的类似操作允许系统控制器通过仍具有超相干数据的处理器触发在共享高速缓存行中发出对于修改数据的Z1读请求。该方法还包括启用具有多个位的加载指令，其中（1）指示所产生的加载请求是否可以接收超相干数据，以及（2）当所述多个比特指示时，超过表示超相干数据的利用的相关性状态所述加载请求可能不利用所述超相干数据。还提供了具有附加位和相关功能的专用存储指令。

77. 发明授权

US07047320B2 Data processing system providing hardware acceleration of input/output (I/O) communication 有权
标题翻译：数据处理系统提供输入/输出（I / O）通讯的硬件加速
公开(公告)号：US07047320B2
公开(公告)日：2006-05-16
申请号：US10339724
申请日：2003-01-09
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F3/00
CPC分类号： G06F13/124 , G06F12/0835
摘要： An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.
摘要翻译：诸如处理单元的集成电路包括衬底和形成在衬底中的集成电路。集成电路包括执行指令的处理器核心，耦合到处理器核心的互连接口，其支持处理器核心与集成电路外部的系统互连之间的通信，以及外部通信适配器的至少一部分，耦合通过输入/输出通信链路支持输入/输出通信的处理器核心。

78. 发明授权

US06910062B2 Method and apparatus for transmitting packets within a symmetric multiprocessor system 失效
标题翻译：用于在对称多处理器系统内传输分组的方法和装置
公开(公告)号：US06910062B2
公开(公告)日：2005-06-21
申请号：US09918812
申请日：2001-07-31
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： H04L12/42 , G06F15/17 , G06F15/16
CPC分类号： G06F15/17
摘要： The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.
摘要翻译：对称多处理器系统包括多个处理节点，每个节点具有多个代理，通过互连彼此连接。请求事务由主节点中的主代理发起到所有接收节点。生成用于与请求事务相关联的写计数器号。主代理然后等待来自接收节点的组合响应。在接收到组合响应之后，根据组合的响应，将数据分组从主代理发送到所有预期的接收节点。在发送数据分组之后，主节点中的主代理准备好发送另一请求事务以及新的写计数器号，而不需要等待来自接收节点的确认。

79. 发明授权

US06671712B1 Multi-node data processing system having a non-hierarchical interconnect architecture 有权
标题翻译：具有非分层互连架构的多节点数据处理系统
公开(公告)号：US06671712B1
公开(公告)日：2003-12-30
申请号：US09436898
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F13/4217
摘要： A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency. The non-hierarchical interconnect architecture also permits design flexibility in that the segment of the interconnect within each node can be independently implemented by a set of buses or as a switch, depending upon cost and performance considerations.
摘要翻译：数据处理系统包括多个节点，每个节点包含至少一个代理，以及节点内的代理可访问的数据存储。多个节点通过包括多个非阻塞单向地址信道和至少一个单向数据信道的非分层互连来耦合。在所有多个地址信道上分别耦合到并且窥探事务的代理只能在相关联的地址信道上发布事务。当前的非分层互连架构采用的单向信道允许高频抽运操作对于传统的双向共享系统总线是不可能的。另外，与传统分层系统相比，由于没有层间（例如，总线采集）通信延迟，与本地高速缓存未命中所产生的远程（高速缓存或主）存储器的访问延迟大大降低。非分层互连架构还允许设计灵活性，因为根据成本和性能考虑，每个节点内的互连部分可以由一组总线或开关单独地实现。

80. 发明授权

US06658556B1 Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction 失效
标题翻译：为存储器访问指令散列目标地址，以便在执行之前确定哪个特定的加载/存储单元处理该指令
公开(公告)号：US06658556B1
公开(公告)日：2003-12-02
申请号：US09364288
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1730
CPC分类号： G06F9/3885 , G06F9/3013 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/384 , G06F9/3891
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.
摘要翻译：处理器包括执行资源，数据存储和与数据存储器和执行资源耦合的指令排序单元，其将数据存储器内的指令提供给执行资源。执行资源包括多个加载存储单元，每个加载存储单元仅处理在地址空间的多个子集中的相应一个子集内访问具有相关联地址的数据的指令。加载存储单元可以具有不同的硬件，使得可以并发执行的最大数量的指令对于不同的加载存储单元是不同的，或者使得一些加载存储单元被限制为执行某些类别的指令。

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