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71. 发明授权

US07732816B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07732816B2
公开(公告)日：2010-06-08
申请号：US11977705
申请日：2007-10-25
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： H01L29/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
摘要翻译：公开了一种半导体集成电路器件，例如存储器件或放射线检测器，其中数据存储单元形成在衬底上。每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷在源和漏之间。

72. 发明授权

US07239549B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07239549B2
公开(公告)日：2007-07-03
申请号：US11132979
申请日：2005-05-19
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中在衬底上形成数据存储单元。每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷在源和漏之间。

73. 发明申请

US20070102705A1 Thin film transistors and semiconductor constructions 失效
标题翻译：薄膜晶体管和半导体结构
公开(公告)号：US20070102705A1
公开(公告)日：2007-05-10
申请号：US11644863
申请日：2006-12-21
申请人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
发明人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
IPC分类号： H01L29/04 , H01L29/786
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译：相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。薄膜晶体管可以被制造为底部门控或顶部门控。可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与多晶薄膜层。

74. 发明授权

US07170807B2 Data storage device and refreshing method for use with such device 有权
标题翻译：数据存储装置和与这种装置一起使用的刷新方法
公开(公告)号：US07170807B2
公开(公告)日：2007-01-30
申请号：US11048387
申请日：2005-02-01
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C7/00 , G11C11/24 , G11C11/34
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
摘要翻译：公开了诸如具有多个数据存储单元10的DRAM存储器的数据存储装置。每个数据存储单元10具有随时间变化并表示两个二进制逻辑状态之一的物理参数。选择电路16，写入电路18和刷新电路22将输入信号施加到数据存储单元，以通过使代表二进制逻辑状态之一的那些单元的至少那些单元的时间的时间来反转物理参数的变化，在所述状态之一的细胞的物理参数比在另一个状态。

75. 发明申请

US20060114717A1 Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
标题翻译：用于浮体存储晶体管，存储单元和存储器阵列的低功耗编程技术
公开(公告)号：US20060114717A1
公开(公告)日：2006-06-01
申请号：US11334338
申请日：2006-01-17
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
摘要翻译：这里描述和说明了许多发明。在一个方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储器单元进行编程，由此存储器单元的电流/功耗很少电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

76. 发明申请

US20060001019A1 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same 有权
公开(公告)号：US20060001019A1
公开(公告)日：2006-01-05
申请号：US11216415
申请日：2005-08-30
申请人： Gurtej Sandhu , Pierre Fazan
发明人： Gurtej Sandhu , Pierre Fazan
IPC分类号： H01L29/06 , H01L29/08
CPC分类号： H01L21/7687 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76895 , H01L27/10852 , H01L27/10855 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.

77. 发明授权

US06982918B2 Data storage device and refreshing method for use with such device 有权
标题翻译：数据存储装置和与这种装置一起使用的刷新方法
公开(公告)号：US06982918B2
公开(公告)日：2006-01-03
申请号：US10487162
申请日：2003-03-17
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/00
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells (10) is disclosed. Each data storage cell (10) has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit (16), writing circuits (18) and a refreshing circuit (22) apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
摘要翻译：公开了诸如具有多个数据存储单元（10）的DRAM存储器的数据存储设备。每个数据存储单元（10）具有随时间变化并表示两个二进制逻辑状态之一的物理参数。选择电路（16），写入电路（18）和刷新电路（22）将输入信号施加到数据存储单元，以通过至少那些表示二进制逻辑状态之一的单元的时间来反转物理参数随时间的变化导致在所述状态之一中的细胞的物理参数的变化比在另一种状态中的不同变化。

78. 发明授权

US06937516B2 Semiconductor device 有权
公开(公告)号：US06937516B2
公开(公告)日：2005-08-30
申请号：US10694689
申请日：2003-10-28
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

79. 发明授权

US06930918B2 Semiconductor device 有权
公开(公告)号：US06930918B2
公开(公告)日：2005-08-16
申请号：US10724648
申请日：2003-12-01
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

80. 发明申请

US20050156240A1 Thin film transistors and semiconductor constructions 失效
标题翻译：薄膜晶体管和半导体结构
公开(公告)号：US20050156240A1
公开(公告)日：2005-07-21
申请号：US11021651
申请日：2004-12-22
申请人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
发明人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/04 , H01L29/786 , H01L21/00 , H01L21/8242
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译：相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。薄膜晶体管可以被制造为底部门控或顶部门控。可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与多晶薄膜层。

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