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71. 发明申请

US20110289485A1 Software Trace Collection and Analysis Utilizing Direct Interthread Communication On A Network On Chip 审中-公开
标题翻译：软件跟踪收集和分析利用网络上的直接间接通信
公开(公告)号：US20110289485A1
公开(公告)日：2011-11-24
申请号：US12784533
申请日：2010-05-21
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/3636
摘要： Collecting and analyzing trace data while in a software debug mode through direct interthread communication (‘DITC’) on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including enabling the collection of software debug information in a selected set of IP blocks distributed through the NOC, each IP block within the selected set of IP blocks having a set of trace data; collecting software debugging information via the set of trace data; communicating the set of trace data to a destination repository; and analyzing the set of trace data at the destination repository.
摘要翻译：在软件调试模式下，通过芯片上的直接通讯（DITC）（“NOC”）收集和分析跟踪数据，NOC包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适应于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及每个网络接口控制器控制通过路由器进行IP间块通信包括能够在通过NOC分配的所选择的一组IP块中收集软件调试信息，所选择的一组IP块中的每个IP块具有一组跟踪数据; 通过一组跟踪数据收集软件调试信息; 将该组跟踪数据传送到目的地存储库; 并分析目标存储库中的一组跟踪数据。

72. 发明授权

US07992043B2 Software debugger for packets in a network on a chip 失效
标题翻译：软件调试器，用于芯片上网络中的数据包
公开(公告)号：US07992043B2
公开(公告)日：2011-08-02
申请号：US12255837
申请日：2008-10-22
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F11/00
CPC分类号： G06F11/362
摘要： A breakpoint packet is dispatched to a Network On A Chip (NOC). The breakpoint packet instructs one or more specified nodes on the NOC to place the specified nodes, or a core or hardware thread within a specified node, to execute in “single step” mode, in order to enable a debugging of a work packet that is dispatched to the specific node.
摘要翻译：断点数据包被分派到片上网络（NOC）。断点包指示NOC上的一个或多个指定节点将指定的节点或指定节点内的核心或硬件线程放置在“单步”模式下执行，以便能够调试工作包调度到特定节点。

73. 发明申请

US20100238169A1 Physical Rendering With Textured Bounding Volume Primitive Mapping 失效
标题翻译：物理渲染与纹理边界体原子映射
公开(公告)号：US20100238169A1
公开(公告)日：2010-09-23
申请号：US12407398
申请日：2009-03-19
申请人： David K. Fowler , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： David K. Fowler , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06T15/40
CPC分类号： G06T15/06 , G06T15/40
摘要： A circuit arrangement, program product and circuit arrangement utilize a textured bounding volume to reduce the overhead associated with generating and using an Accelerated Data Structure (ADS) in connection with physical rendering. In particular, a subset of the primitives in a scene may be mapped to surfaces of a bounding volume to generate textures on such surfaces that can be used during physical rendering. By doing so, the primitives that are mapped to the bounding volume surfaces may be omitted from the ADS to reduce the processing overhead associated with both generating the ADS and using the ADS during physical rendering, and furthermore, in many instances the size of the ADS may be reduced, thus reducing the memory footprint of the ADS, and often improving cache hit rates and reducing memory bandwidth.
摘要翻译：电路布置，程序产品和电路布置利用纹理边界体积来减少与生成和使用结合物理渲染的加速数据结构（ADS）相关联的开销。特别地，场景中的图元的子集可被映射到边界体积的表面，以在物理渲染期间使用的这些表面上生成纹理。通过这样做，可以从ADS中省略映射到边界体积表面的原语，以减少在物理渲染期间生成ADS和使用ADS相关联的处理开销，此外，在许多情况下，ADS的大小可以减少，从而减少ADS的内存占用，并且经常提高缓存命中率并减少内存带宽。

74. 发明申请

US20100191940A1 SINGLE STEP MODE IN A SOFTWARE PIPELINE WITHIN A HIGHLY THREADED NETWORK ON A CHIP MICROPROCESSOR 失效
标题翻译：芯片微处理器中的高度线性化网络中的软件管道中的单步模式
公开(公告)号：US20100191940A1
公开(公告)日：2010-07-29
申请号：US12358776
申请日：2009-01-23
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/32
CPC分类号： G06F9/3844 , G06F9/30174 , G06F9/3806 , G06F11/3636 , G06F11/3648
摘要： A hardware thread is selectively forced to single step the execution of software instructions from a work packet granule. A “single step” packet is associated with a work packet granule. The work packet granule, with the associated “single step” packet, is dispatched as an appended work packet granule to a preselected hardware thread in a processor core, which, in one embodiment, is located at a node in a Network On a Chip (NOC). The work packet granule then executes in a single step mode until completion.
摘要翻译：有选择地强制硬件线程从工作包颗粒单步执行软件指令。 “单步”包与工作包颗粒相关联。具有相关联的“单步”分组的工作分组粒子被作为附加的工作分组粒子被分派到处理器核心中的预选硬件线程，在一个实施例中，其在一个实施例中位于网络片上（ NOC）。工作包颗粒然后以单步模式执行直到完成。

75. 发明申请

US20100188402A1 User-Defined Non-Visible Geometry Featuring Ray Filtering 有权
标题翻译：用户定义的不可见几何特征射线滤波
公开(公告)号：US20100188402A1
公开(公告)日：2010-07-29
申请号：US12360989
申请日：2009-01-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T15/50
CPC分类号： G06T15/06
摘要： A method, system and computer program product for managing secondary rays during ray-tracing are presented. A non-visible unidirectional ray tracing object logically surrounds a user-selected virtual object in a computer generated illustration. This unidirectional ray tracing object prevents secondary tracing rays from emanating from the user-selected virtual object during ray tracing.
摘要翻译：提出了一种在射线跟踪期间管理二次射线的方法，系统和计算机程序产品。在计算机生成的图示中，不可见的单向光线跟踪对象在逻辑上围绕用户选择的虚拟对象。这种单向光线跟踪对象可防止在光线跟踪期间从用户选择的虚拟对象发出辅助跟踪光线。

76. 发明申请

US20090282227A1 Monitoring Software Pipeline Performance On A Network On Chip 失效
标题翻译：监控网络芯片上的软件流水线性能
公开(公告)号：US20090282227A1
公开(公告)日：2009-11-12
申请号：US12117875
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/30
CPC分类号： G06F11/3404 , G06F15/7825
摘要： Software pipelining on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers. Embodiments of the present invention include implementing a software pipeline on the NOC, including segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; executing each stage of the software pipeline on a thread of execution on an IP block; monitoring software pipeline performance in real time; and reconfiguring the software pipeline, dynamically, in real time, and in dependence upon the monitored software pipeline performance.
摘要翻译：芯片上的软件流水线（NOC），NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和路由器网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器。本发明的实施例包括在NOC上实现软件管线，包括将计算机软件应用程序分阶段分段，每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块; 在IP块上执行一个执行线程的软件流水线的每个阶段; 实时监控软件流水线性能; 并且动态地，实时地重新配置软件流水线，并且依赖于监视的软件流水线性能。

77. 发明申请

US20090125703A1 Context Switching on a Network On Chip 审中-公开
标题翻译：上下文切换网络上的芯片
公开(公告)号：US20090125703A1
公开(公告)日：2009-05-14
申请号：US11937579
申请日：2007-11-09
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/461 , G06F15/7825
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox, each IP block also including a stack normally used for context switching, the stack access slower than the outbox access, and each IP block further including a processor supporting a plurality of threads of execution, the processor configured to save, upon a context switch, a context of a current thread of execution in memory locations in a memory array in the outbox instead of the stack and lock the memory locations in which the context was saved.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”）上的数据处理，每个IP块通过存储器通信控制器和网络适配于路由器接口控制器，每个IP块还通过包含收件箱和发件箱的低延迟，高带宽应用消息互连来适应网络，每个IP块还包括通常用于上下文切换的堆栈，堆栈访问比发送端口访问慢并且每个IP块还包括支持多个执行线程的处理器，所述处理器被配置为在上下文切换时将所述执行的当前线程的上下文保存在所述发件箱中的存储器阵列中的存储器位置中，而不是所述堆栈并锁定保存上下文的内存位置。

78. 发明申请

US20080133489A1 RUN-TIME PERFORMANCE VERIFICATION SYSTEM 审中-公开
标题翻译：运行性能验证系统
公开(公告)号：US20080133489A1
公开(公告)日：2008-06-05
申请号：US12018329
申请日：2008-01-23
申请人： Thomas M. Armstead , Lance R. Meyer , Paul E. Schardt , Robert A. Shearer
发明人： Thomas M. Armstead , Lance R. Meyer , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F7/10 , G06F17/30
CPC分类号： G06F11/3414 , G06F11/3452 , G06F11/3476 , G06F11/349 , G06F2201/86 , H04L43/16
摘要： A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.
摘要翻译：允许捕获互连总线上的设备之间基于分组的通信事务以测量性能的方法和装置。性能指标可以通过在各个位置通过系统捕获事件来确定。可以通过计算捕获事件的性能指标并将这些度量与预定义的性能范围和/或自学习性能范围进行比较，从而在运行时验证性能。此外，本发明的实施例提供了对总线业务的动态定制以产生潜在的故障状况。对于一些实施例，可以在模拟环境中执行如本文所述的性能验证。

79. 发明授权

US09292965B2 Accelerated data structure positioning based upon view orientation 有权
标题翻译：基于视图方向加速数据结构定位
公开(公告)号：US09292965B2
公开(公告)日：2016-03-22
申请号：US12407340
申请日：2009-03-19
申请人： David K. Fowler , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： David K. Fowler , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06T17/00 , G06T15/06 , G06T15/40
CPC分类号： G06T17/005 , G06T15/06 , G06T15/40
摘要： A circuit arrangement, program product and circuit arrangement utilize the known view orientation for an image frame to be rendered to reposition an Accelerated Data Structure (ADS) used during rendering to optimize the generation and/or use of the ADS, e.g., by transforming a scene from which an image frame is rendered to orient the scene relative to the view orientation prior to generating the ADS. A scene may be transformed, for example, to orient the view orientation within a single octant of the scene, with additional processing resources assigned to that octant to ensure sufficient processing resources are devoted to processing the primitives within the view orientation.
摘要翻译：电路布置，程序产品和电路布置利用已知的视图方向来渲染图像帧以重新定位在渲染期间使用的加速数据结构（ADS），以优化ADS的生成和/或使用，例如通过将在生成ADS之前，渲染图像帧以使场景相对于视图方向定向的场景。例如，可以将场景变换为将景物方向定向在场景的单个八分圆内，附加的处理资源被分配给该八分圆，以确保足够的处理资源用于在视图取向中处理图元。

80. 发明授权

US09251116B2 Direct interthread communication dataport pack/unpack and load/save 有权
标题翻译：直接interthread通信数据端口包/解包和加载/保存
公开(公告)号：US09251116B2
公开(公告)日：2016-02-02
申请号：US13307609
申请日：2011-11-30
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/78
CPC分类号： G06F15/7832 , G06F15/7825
摘要： A circuit arrangement, method, and program product for compressing and decompressing data in a node of a system including a plurality of nodes interconnected via an on-chip network. Compressed data may be received and stored at an input buffer of a node, and in parallel with moving the compressed data to an execution register of the node, decompression logic of the node may decompress the data to generate uncompressed data, such that uncompressed data is stored in the execution register for utilization by an execution unit of the node. Uncompressed data may be output by the execution unit into the execution register, and in parallel with moving the uncompressed data to an output buffer of the node connected to the on-chip network, compression logic may compress the uncompressed data to generate compressed data, such that compressed data is stored at the output buffer.
摘要翻译：一种用于在包括通过片上网络互连的多个节点的系统的节点中压缩和解压缩数据的电路装置，方法和程序产品。压缩数据可以被接收并存储在节点的输入缓冲器处，并且与将压缩数据移动到节点的执行寄存器并行地，节点的解压缩逻辑可以解压缩数据以生成未压缩数据，使得未压缩数据为存储在执行寄存器中以供节点的执行单元利用。未经压缩的数据可以由执行单元输出到执行寄存器中，并且与将未压缩数据移动到连接到片上网络的节点的输出缓冲器并行地，压缩逻辑可压缩未压缩数据以产生压缩数据，该压缩数据被存储在输出缓冲器中。

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