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71. 发明授权

US06963112B2 Electrostatic discharge protection circuit with a diode string 失效
标题翻译：具有二极管串联的静电放电保护电路
公开(公告)号：US06963112B2
公开(公告)日：2005-11-08
申请号：US10754770
申请日：2004-01-09
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L23/60 , H01L23/62 , H01L27/02 , H01L29/76
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit is disclosed for preventing a pad-to-pad ESD charge. The protection circuit for each pad of an integrated circuit comprises a current dissipation module with an N-type MOSFET connected in parallel with a bipolar junction transistor (BJT) wherein the drain of the MOSFET and the collector of the BJT are connected to a first common node and the source of the MOSFET and the emitter of the BJT are connected to a second common node connectable to a second operating voltage. A diode string is connected to a first pad at its anode end having a total forward voltage drop more than a first operating voltage and with its cathode end connected to the body of the MOSFET, the base of the BJT, and to the second common node through a resistor.
摘要翻译：公开了一种静电放电（ESD）保护电路，用于防止焊盘到焊盘ESD电荷。用于集成电路的每个焊盘的保护电路包括具有与双极结型晶体管（BJT）并联连接的N型MOSFET的电流耗散模块，其中MOSFET的漏极和BJT的集电极连接到第一公共端节点和MOSFET的源极和BJT的发射极连接到可连接到第二工作电压的第二公共节点。二极管串在其阳极端连接到第一焊盘，其具有大于第一工作电压的总正向压降，其阴极端连接到MOSFET的主体，BJT的基极和第二公共节点通过一个电阻。

72. 发明申请

US20050207211A1 Programmable MOS device formed by hot carrier effect 有权
标题翻译：可编程MOS器件由热载体形成
公开(公告)号：US20050207211A1
公开(公告)日：2005-09-22
申请号：US10803785
申请日：2004-03-17
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G11C11/00 , G11C11/401 , G11C11/4063 , G11C16/12
CPC分类号： G11C16/10
摘要： A programmable metal-oxide-semiconductor (MOS) memory circuit and the method for programming same and disclosed. The circuit comprises a first N-type transistor having a gate region tied with a drain region and connectable to a first control voltage level, and a source region connected to a second voltage level; and a second N-type transistor having a gate region tied with a drain region and connectable to the first control voltage level, and a source region connected to the second voltage level, wherein the first and second control voltage levels are imposed to program either the first or second N-type transistor by causing a voltage difference between the drain region and the source region (Vds) and voltage difference between the gate region and the source region (Vgs) to be bigger than a predetermined threshold voltage to induce a hot carrier effect.
摘要翻译：一种可编程金属氧化物半导体（MOS）存储器电路及其编程方法，并公开。该电路包括第一N型晶体管，其栅极区域与漏极区域连接并可连接到第一控制电压电平，以及源极区域连接到第二电压电平; 以及第二N型晶体管，其具有与漏极区域连接并可连接到第一控制电压电平的栅极区域，以及连接到第二电压电平的源极区域，其中施加第一和第二控制电压电平以对通过使漏极区域和源极区域之间的电压差（Vds）和栅极区域与源极区域（Vgs）之间的电压差大于预定的阈值电压来引起热载流子，从而使第一或第二N型晶体管影响。

73. 发明申请

US20050185441A1 Programmable MOS device formed by stressing polycrystalline silicon 失效
标题翻译：通过应力多晶硅形成的可编程MOS器件
公开(公告)号：US20050185441A1
公开(公告)日：2005-08-25
申请号：US10784705
申请日：2004-02-23
申请人： Chung-Hui Chen , Shun-Liang Hsu , Yean-Kuen Fang
发明人： Chung-Hui Chen , Shun-Liang Hsu , Yean-Kuen Fang
IPC分类号： G11C17/00 , G11C17/14
CPC分类号： G11C17/14
摘要： A programmable memory circuit and a method for programming the same are disclosed. A polycrystalline silicon resistor pair are used in a programmable memory cell. The pair includes a first polycrystalline silicon resistor stressable by a predetermined current thereacross, and a second polycrystalline silicon resistor similarly structured as the first polycrystalline silicon resistor stressable by the predetermined current, wherein when only the first resistor is stressed by the predetermined current, a resistance of the first resistor is lowered as compared to the unstressed second resistor, thereby programming the memory cell.
摘要翻译：公开了一种可编程存储器电路及其编程方法。在可编程存储器单元中使用多晶硅电阻器对。该对包括可以通过其中的预定电流强制的第一多晶硅电阻器和类似于由预定电流压力的第一多晶硅电阻器构成的第二多晶硅电阻器，其中当只有第一电阻器被预定电流施加时，电阻与未应力的第二电阻器相比降低第一电阻器，从而对存储器单元进行编程。

74. 发明申请

US20050055647A1 System and method for switching software functions 审中-公开
标题翻译：用于切换软件功能的系统和方法
公开(公告)号：US20050055647A1
公开(公告)日：2005-03-10
申请号：US10812873
申请日：2004-03-31
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G06F3/048 , G09G5/00
CPC分类号： G06F3/0482 , G06F3/0489
摘要： A software function switching method and a system using the same that allows the user to set and operate a group of keys in an input unit as the hotkey sequence for switching and opening the sub-menu functions of application software. The user only needs to repeatedly press the first key of the hotkey sequence, and then intermittently press the second key of the hotkey sequence to send the input signals via the input unit into a data processing system. This method and system instructs the data processing system to count the number of times the user has pressed the hotkey, and, according to the count value, diagrams on the display unit corresponding to the sub-menu functions of the application software are sequentially switched and opened. When switched to the diagram for the sub-menu function that the user wishes to open, the first key of the hotkey is released, and the sub-menu function represented by the diagram can be opened. This allows the user to sequentially switch to and open every sub-menu function of the application software using only a set of hotkeys.
摘要翻译：一种软件功能切换方法及使用该软件功能切换方法的系统，其特征在于，允许用户将输入单元中的一组键设置和操作为用于切换和打开应用软件的子菜单功能的热键序列。用户只需要反复按热键序列的第一个键，然后间歇地按下热键序列的第二个键，通过输入单元将输入信号发送到数据处理系统中。该方法和系统指示数据处理系统对用户按下热键的次数进行计数，并且根据计数值，依次切换与应用软件的子菜单功能对应的显示单元上的图，开了当切换到用户希望打开的子菜单功能的图表时，热键的第一个键被释放，并且可以打开由图表示的子菜单功能。这允许用户仅使用一组热键顺序地切换并打开应用软件的每个子菜单功能。

75. 发明授权

US06638793B1 Methodology to pack standard staggered bond input-output buffer into linear input-output buffer 有权
标题翻译：将标准交错键输入输出缓冲器包装到线性输入输出缓冲器中的方法
公开(公告)号：US06638793B1
公开(公告)日：2003-10-28
申请号：US10086260
申请日：2002-03-04
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L2144
CPC分类号： H01L23/5286 , H01L23/50 , H01L24/06 , H01L2224/05554 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01075 , H01L2924/14 , H01L2924/00
摘要： A new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad I/O buffers and the linearly arranged bond pads is achieved by a frame design that sequentially connects the staggered bond pad I/O buffers to the linearly arranged bond pads.
摘要翻译：提供了一种新的方法，允许将交错键I / O缓冲器放置或堆叠到线性键I / O缓冲器中。接合焊盘是线性布置的，交错键合焊盘I / O缓冲器和线性布置的接合焊盘之间的界面是通过将交错的焊盘I / O缓冲器顺序地连接到线性布置的接合焊盘的框架设计来实现的。

76. 发明授权

US06414534B1 Level shifter for ultra-deep submicron CMOS designs 有权
公开(公告)号：US06414534B1
公开(公告)日：2002-07-02
申请号：US09784819
申请日：2001-02-20
申请人： Wen-Tai Wang , Chung-Hui Chen
发明人： Wen-Tai Wang , Chung-Hui Chen
IPC分类号： H03L500
CPC分类号： H03K3/012 , H03K3/356113 , H03K3/356182
摘要： New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output. A third NMOS transistor has the gate tied to the first NMOS drain, v source tied to the level shifting input, and the drain tied to the level shifting output. A fourth NMOS transistor has the gate tied to the second NMOS drain, the source tied to the inverted level shifting input, and the drain tied to the first NMOS drain.

77. 发明授权

US06414524B1 Digital output buffer for MOSFET device 有权
标题翻译： MOSFET器件的数字输出缓冲器
公开(公告)号：US06414524B1
公开(公告)日：2002-07-02
申请号：US09812517
申请日：2001-03-20
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H03K300
CPC分类号： H03K17/164
摘要： A digital output buffer for an integrated circuit such as a MOSFET includes slew rate control and reduced crowbar current. The buffer includes pull-up and pull-down networks coupled between the input and output of the buffer. Each of the networks includes a plurality of conductive switch elements that are sequentially turned on or off by means of RC networks that control the switching delay between the conductive switch elements, and thus the slew rate of the buffer. The RC network includes a plurality of unbalanced passgates, each of which includes a high resistance and a low resistance that can be selectively coupled into circuit with the conductive switch elements so as to better control the timing of the turn on and turn off of the network, and thereby reduce crowbar currents.
摘要翻译：用于诸如MOSFET的集成电路的数字输出缓冲器包括压摆率控制和减少的消弧电流。缓冲器包括耦合在缓冲器的输入和输出之间的上拉和下拉网络。每个网络包括多个导电开关元件，其通过控制导电开关元件之间的开关延迟的RC网络依次导通或关断，从而缓冲器的转换速率。 RC网络包括多个不平衡传送门，每个不平衡传递门包括高电阻和低电阻，其可以选择性地与导电开关元件耦合到电路中，以便更好地控制网络的接通和断开的定时，从而减少撬棒电流。

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