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71. 发明申请

US20090130864A1 SYSTEMS AND METHODS FOR FLASH ANNEALING OF SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于半导体器件闪光退火的系统和方法
公开(公告)号：US20090130864A1
公开(公告)日：2009-05-21
申请号：US11942367
申请日：2007-11-19
申请人： Narendra Singh MEHTA , Perry Howard Shields , Amitabh Jain
发明人： Narendra Singh MEHTA , Perry Howard Shields , Amitabh Jain
IPC分类号： H01L21/02 , F27D11/00
CPC分类号： H01L29/78 , H01L21/28176 , H01L21/324
摘要： An embodiment generally relates a method of processing semiconductor devices. The method includes forming a semiconductor device and exposing the semiconductor device to a temperature substantially between 1175 to 1375 degrees Celsius after the formation of a gate dielectric layer. The method also includes annealing the semiconductor device for a period of time.
摘要翻译：实施例通常涉及半导体器件的处理方法。该方法包括形成半导体器件，并且在形成栅极电介质层之后将半导体器件暴露于基本上在1175至1375摄氏度之间的温度。该方法还包括半导体器件退火一段时间。

72. 发明授权

US07479668B2 Source/drain extension implant process for use with short time anneals 有权
标题翻译：源/漏扩展植入过程用于短时间退火
公开(公告)号：US07479668B2
公开(公告)日：2009-01-20
申请号：US11370339
申请日：2006-03-08
申请人： Amitabh Jain , Gordon Pollack
发明人： Amitabh Jain , Gordon Pollack
IPC分类号： H01L31/112
CPC分类号： H01L21/26586 , H01L21/324 , H01L21/823814 , H01L29/6659 , H01L29/7833
摘要： The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).
摘要翻译：本发明在一个实施例中提供一种用于制造金属氧化物半导体（MOS）器件（100）的工艺。该方法包括在衬底（105）上形成栅极（120）并在衬底（105）中形成源极/漏极延伸部分（160）。形成源极/漏极延伸部分（160）包括异常倾斜的掺杂剂注入（135）和掺杂剂注入（145）。异常倾斜的掺杂剂注入（135）使用大于约零度的第一加速能量和倾斜角。掺杂剂注入（145）使用高于第一加速能量的第二加速能量。该工艺还包括执行衬底（105）的超高温退火，其中源极/漏极延伸部（160）的部分（170）在栅极（120）下方。

73. 发明授权

US07345355B2 Complementary junction-narrowing implants for ultra-shallow junctions 有权
标题翻译：用于超浅交叉点的互补连接收缩植入物
公开(公告)号：US07345355B2
公开(公告)日：2008-03-18
申请号：US10942607
申请日：2004-09-15
申请人： Amitabh Jain , Stephanie W. Butler
发明人： Amitabh Jain , Stephanie W. Butler
IPC分类号： H01L29/00 , H01L31/0288
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/1083 , H01L29/7833
摘要： Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.
摘要翻译：公开了使用多个离子注入步骤在半导体衬底中形成超浅结的方法。离子注入步骤包括植入至少一种电子活性掺杂剂以及通过在掺杂剂注入期间通过沟槽化和/或通过热扩散来有效地限制结扩展的至少两种物质的注入。在掺杂剂注入之后，电子活性掺杂剂通过热处理而被激活。

74. 发明申请

US20070049022A1 NICKEL ALLOY SILICIDE INCLUDING INDIUM AND A METHOD OF MANUFACTURE THEREFOR 有权
标题翻译：镍合金硅胶包括其中的一种和其制造方法
公开(公告)号：US20070049022A1
公开(公告)日：2007-03-01
申请号：US11551374
申请日：2006-10-20
申请人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
发明人： Peijun Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

75. 发明授权

US07163878B2 Ultra-shallow arsenic junction formation in silicon germanium 有权
标题翻译：硅锗中的超浅砷结点形成
公开(公告)号：US07163878B2
公开(公告)日：2007-01-16
申请号：US11267413
申请日：2005-11-04
申请人： Puneet Kohli , Mark Rodder , Rick Wise , Amitabh Jain
发明人： Puneet Kohli , Mark Rodder , Rick Wise , Amitabh Jain
IPC分类号： H01L21/265
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).
摘要翻译：一方面，本发明提供一种在硅 - 锗层（20）中形成结的方法。在该特定实施例中，该方法包括将掺杂剂（80）注入到硅 - 锗层（20）中并将氟（70）注入到硅 - 锗层（20）中。

76. 发明授权

US07118980B2 Solid phase epitaxy recrystallization by laser annealing 有权
标题翻译：激光退火固相外延再结晶
公开(公告)号：US07118980B2
公开(公告)日：2006-10-10
申请号：US10972872
申请日：2004-10-25
申请人： Amitabh Jain
发明人： Amitabh Jain
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/268 , H01L29/6656 , H01L29/6659
摘要： Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial recrystallization is performed within the drain extensions utilizing a laser SPER annealing process in the manufacture of semiconductor products. One method (70) includes a preamorphizing process (74) of implanting a heavy ion species such as Germanium deep into an extension region of a substrate adjacent a channel region of the substrate to form a deep amorphized region, then implanting boron or another such dopant species into an extension region of the substrate adjacent the channel region. The implanted dopant is then preannealed (78) at a low temperature to set the junction depth and doping concentration. The extensions and/or the deep source/drain regions are subsequently annealed (84) with a laser at a high temperature providing a solid phase epitaxial recrystallization in the regions proximate the channel region to achieve ultra high doping concentrations and activation levels with an abrupt gradient.
摘要翻译：描述了用于制造用于MOS型晶体管的浅的和突然的梯度漏极延伸的方法（70），其中在半导体产品的制造中利用激光SPER退火工艺在漏极延伸内进行固相外延重结晶。一种方法（70）包括将邻近衬底的沟道区域的衬底中的重离子物质（例如锗）深深地注入到衬底的延伸区域中以形成深非晶化区域的前变质化工艺（74），然后将硼或另一种这样的掺杂剂物质进入邻近沟道区的衬底的延伸区域。然后将注入的掺杂剂在低温下预退火（78）以设定结深度和掺杂浓度。随后在高温下用激光退火延伸部分和/或深源极/漏极区域（84），从而在靠近沟道区域的区域提供固相外延重结晶，以实现超高掺杂浓度和具有突变梯度的激活水平。

77. 发明申请

US20050112830A1 Ultra shallow junction formation 审中-公开
标题翻译：超浅结结形成
公开(公告)号：US20050112830A1
公开(公告)日：2005-05-26
申请号：US10816776
申请日：2004-04-02
申请人： Amitabh Jain , Lance Robertson
发明人： Amitabh Jain , Lance Robertson
IPC分类号： H01L21/265 , H01L21/324 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/324 , H01L29/6659
摘要： The invention describes a method for forming ultra shallow junction formation. Dopant species are implanted into a semiconductor. Solid phase epitaxy anneals and subsequent ultra high temperature anneals are performed following the implantation processes.
摘要翻译：本发明描述了形成超浅结结形成的方法。将掺杂物质注入到半导体中。在植入过程之后进行固相外延退火和随后的超高温退火。

78. 发明授权

US06677201B1 Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors 有权
标题翻译：制造用于金属氧化物半导体晶体管的热CVD氮氧化物和BTBAS氮化物侧壁间隔物的方法
公开(公告)号：US06677201B1
公开(公告)日：2004-01-13
申请号：US10261407
申请日：2002-10-01
申请人： Haowen Bu , Amitabh Jain
发明人： Haowen Bu , Amitabh Jain
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/3145 , H01L29/6656 , H01L29/7833
摘要： A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer (110) and a silicon nitride layer (120) are used to form sidewalls for MOS transistors. The silicon nitride layer (120) is formed using BTBAS processes.
摘要翻译：在MOS晶体管制造工艺中在侧壁形成工艺期间使用CVD氮氧化物和BTBAS氮化物的方法。氧氮化硅层（110）和氮化硅层（120）用于形成MOS晶体管的侧壁。使用BTBAS工艺形成氮化硅层（120）。

79. 发明授权

US08691644B2 Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor 有权
标题翻译：用应力通道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法
公开(公告)号：US08691644B2
公开(公告)日：2014-04-08
申请号：US13541957
申请日：2012-07-05
申请人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
发明人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
摘要翻译：形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

80. 发明申请

US20130009251A1 OFFSET SCREEN FOR SHALLOW SOURCE/DRAIN EXTENSION IMPLANTS, AND PROCESSES AND INTEGRATED CIRCUITS 有权
标题翻译：用于较短的源/漏电延伸植入物的偏移屏幕，以及处理和集成电路
公开(公告)号：US20130009251A1
公开(公告)日：2013-01-10
申请号：US13484592
申请日：2012-05-31
申请人： Amitabh Jain
发明人： Amitabh Jain
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/66 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.
摘要翻译：集成电路制造的过程包括在栅极叠层上提供（32,33）间隔物，以在沟道区域上提供水平偏移，用于在半导体中另外存储（35）一个PLDD注入剂量的直接应用（34）密封物质以垂直地提供屏幕厚度，从而增加栅极堆叠上的间隔物，以提供与栅极堆叠水平的增加的偏移，并形成没有蚀刻的水平屏幕，并且随后提供（36）用于NLDD形成的NLDD注入剂量。还公开了各种集成电路结构，装置和其它制造工艺以及测试过程。

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