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71. 发明授权

US06198816B1 Capacitively coupled ring detector with power provided across isolation barrier 失效
标题翻译：电容耦合环形探测器，提供跨隔离屏障的电源
公开(公告)号：US06198816B1
公开(公告)日：2001-03-06
申请号：US09034428
申请日：1998-03-04
申请人： Jerrell P. Hein , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jerrell P. Hein , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04M1738
CPC分类号： H04L25/06 , H04L7/033 , H04L25/0266 , H04M1/573 , H04M11/06 , H04M19/001 , H04M19/02
摘要： A communication system is provided with a capacitive isolation barrier in which at least a portion of the ring detection circuits may be integrated into the line side circuitry. Moreover the ring detection circuits on the phone line side of the isolation barrier may be powered at least in part by power transmitted from the powered side of the isolation barrier to the phone line side of the isolation barrier through the barrier capacitors. A capacitive interface may directly connect the ringer circuitry on the phone line side of the barrier to the TIP/RING lines. The capacitive interface operates to linearly attenuate the TIP/RING signal voltage levels from the high phone line levels to levels within integrated circuit technology limitations.
摘要翻译：通信系统设置有电容隔离屏障，其中至少一部分环形检测电路可以集成到线路侧电路中。此外，隔离屏障的电话线路侧的环路检测电路可以至少部分地通过从隔离屏障的电源侧通过阻挡电容器传输到隔离屏障的电话线侧的功率供电。电容接口可以将屏障的电话线路上的振铃电路直接连接到TIP / RING线路。电容接口用于将TIP / RING信号电压电平从高电话线路电平线性衰减到集成电路技术限制内的电平。

72. 发明授权

US6167134A External resistor and method to minimize power dissipation in DC holding circuitry for a communication system 失效
标题翻译：外部电阻和方法，以减少通信系统直流保持电路中的功耗
公开(公告)号：US6167134A
公开(公告)日：2000-12-26
申请号：US34683
申请日：1998-03-04
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H03M1/42 , H04L7/033 , H04L25/02 , H04L25/06 , H04M1/57 , H04M11/06 , H04M19/00 , H04M19/02 , H04M1/00
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M11/06 , H04M19/001 , H04M19/02
摘要： A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.
摘要翻译：公开了用于直接存取布置（DAA）电路中的DC保持电路的CMOS实现，其提供期望的电感性能，同时最小化CMOS集成电路所需的功率耗散，特别是在高回路电流下。所公开的直流保持电路可以包括位于CMOS集成电路上的MOS晶体管和用于耗散CMOS集成电路外部的功率的片外功耗电阻器。所公开的CMOS实现还允许用于绘制DC电流的路径来为CMOS集成电路中的其它CMOS电路（例如，ADC和DAC）供电。

73. 发明授权

US6137827A Isolation system with digital communication across a capacitive barrier 失效
公开(公告)号：US6137827A
公开(公告)日：2000-10-24
申请号：US841409
申请日：1997-04-22
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04B3/00 , H04L7/033 , H04L25/00 , H04L25/02 , H04L25/06 , H04M11/06 , H04B13/02
CPC分类号： H04L25/0266 , H04L25/06 , H04M11/06 , H04L7/033
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

74. 发明授权

US6107948A Analog isolation system with digital communication across a capacitive barrier 有权
标题翻译：模拟隔离系统，通过电容屏障进行数字通讯
公开(公告)号：US6107948A
公开(公告)日：2000-08-22
申请号：US316808
申请日：1999-05-21
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04B14/06 , H04L7/033 , H04L25/06 , H04M11/06 , H03M3/02
CPC分类号： H04B14/062 , H04L25/0266 , H04L25/06 , H04M11/06 , H04L7/033
摘要： As isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.
摘要翻译：提供适用于电话，医疗仪器仪表，工业过程控制等应用的隔离系统。本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。最后，提供双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和帧信息在时间上多路复用的数字delta-sigma数据信号组成。

75. 发明授权

US5258758A DAC shutdown for low power supply condition 失效
标题翻译： DAC关断低电源条件
公开(公告)号：US5258758A
公开(公告)日：1993-11-02
申请号：US648791
申请日：1991-01-31
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03M1/06 , H02H3/24 , H03M1/00 , H03M1/66
CPC分类号： H03M1/002 , H02H3/24 , H03M1/66 , Y10T307/858
摘要： A digital-to-analog converter for operating in a low power condition includes a delta-sigma modulator (10) for converting an n-bit digital input signal to an m-bit digital output signal. The output signal is filtered with a switched-capacitor filter (12) and an active RC low-pass filter (18). A low power supply detect circuit receives two power supply input voltages, the low and the high power supplies, and outputs a control signal on a line (38) indicating a low power supply condition. The digital-to-analog converter includes an output stage (26) with the analog output thereof being connected to an analog output terminal (30). A switch (28) is provided for connecting the output stage to the analog output terminal (30) in normal operating mode. In a low power mode, the low power detect circuit (20) generates a control signal on line (38) in response to the power supply voltage falling below a predetermined threshold. The switch (28) is opened and a shunt switch (32) provides a squelch operation by being configured in a closed configuration during a low power condition. Alternately, the output stage (26) can be powered down in the low power condition.
摘要翻译：用于在低功率状态下工作的数模转换器包括用于将n位数字输入信号转换成m位数字输出信号的Δ-Σ调制器（10）。输出信号用开关电容滤波器（12）和有源RC低通滤波器（18）滤波。低电源检测电路接收两个电源输入电压，即低电源和高电源，并且在指示低电源条件的线路（38）上输出控制信号。数模转换器包括其模拟输出连接到模拟输出端（30）的输出级（26）。提供了一个开关（28），用于在正常操作模式下将输出级与模拟输出端（30）相连。在低功率模式下，响应于电源电压低于预定阈值，低功率检测电路（20）在线（38）上产生一个控制信号。开关（28）打开，并且分流开关（32）通过在低功率状态下被配置为闭合配置来提供静噪操作。或者，输出级（26）可以在低功率状态下掉电。

76. 发明授权

US5245344A High order switched-capacitor filter with DAC input 失效
标题翻译：具有DAC输入的高阶开关电容滤波器
公开(公告)号：US5245344A
公开(公告)日：1993-09-14
申请号：US641183
申请日：1991-01-15
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03H19/00 , H03M1/66 , H03M3/02 , H03M7/00
CPC分类号： H03H19/004
摘要： A digital-to-analog converter includes a delta-sigma modulator (10) that receives a digital input and converts it to a one-bit digital output stream. A fourth order switched-capacitor filter (12) is operable to receive the one-bit digital stream and convert it to an analog value int he sampled data domain. This is input to a switched-capacitor/continuous time buffer (14) which is then filtered by an active low pass filter (18) to provide an analog output. The switched-capacitor filter (12) includes four stages of integration (24), (30), (34) and (38). A one-bit DAC (20) is provided for converting the one-bit digital stream to an analog value. The one-bit DAC (20) is integral with the first stage of integration and is summed by a summing junction (22) with the output of the forth stage of integration (38). In this manner, the first stage of integration (24) is operable to influence or reduce the noise output by the fourth stage of integration (38), thus resulting in a low noise high order switched-capacitor filter.
摘要翻译：数模转换器包括接收数字输入并将其转换为1位数字输出流的Δ-Σ调制器（10）。第四级开关电容滤波器（12）可操作以接收一比特数字流并将其转换成采样数据域中的模拟值。这被输入到开关电容器/连续时间缓冲器（14），然后由有源低通滤波器（18）进行滤波以提供模拟输出。开关电容滤波器（12）包括四级积分（24），（30），（34）和（38）。提供一位DAC（20），用于将一位数字流转换为模拟值。一比特DAC（20）与第一级积分是积分的，并且通过求和结（22）与第四级积分（38）的输出相加。以这种方式，第一级积分（24）可操作以影响或降低第四级积分（38）的噪声输出，从而导致低噪声高阶开关电容滤波器。

77. 发明授权

US5087914A DC calibration system for a digital-to-analog converter 失效
标题翻译：用于数模转换器的直流校准系统
公开(公告)号：US5087914A
公开(公告)日：1992-02-11
申请号：US571375
申请日：1990-08-22
申请人： Navdeep S. Sooch , Jeffrey W. Scott , Tadashi Tanaka
发明人： Navdeep S. Sooch , Jeffrey W. Scott , Tadashi Tanaka
IPC分类号： H03M1/10 , H03H17/00 , H03H17/02 , H03M3/02
CPC分类号： H03M3/384 , H03M3/50
摘要： A calibration system for a digital-to-analog converter (DAC) includes a digital portion (10) having a interpolation section (14) for receiving the digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modulator (16) to allow an offset voltage to be summed therewith. The offset value is stored in an offset register (26), which is controlled by a calibration control circuit (40). The output of the delta-sigma modulator (16) is input to an analog section (12), which is comprised of an analog filter (22) and an output amplifier (28). The output amplifier (28) is operable to sample the output of the analog filter (22) and feed this back to a gate (38). The gate (38) is activated during a calibration cycle to feed the comparator output back to the calibration control circuit (40). During the calibration cycle, the output is isolated by an isolation amplifier (32 ) and the analog output pad connected to ground by a switch (44) to provide a low impedance output on the analog output. The calibration control circuit (40) is operable to perform a binary search while sampling the output of the analog section (12) with the input to the interpolation circuit (14) forced to a logic low.
摘要翻译：用于数模转换器（DAC）的校准系统包括具有用于接收数字输入并将其采样频率增加以用于输入到Δ-Σ调制器（16）的内插部分（14）的数字部分（10）。在插值电路（14）和Δ-Σ调制器（16）之间设置求和结（24），以允许偏移电压与其相加。偏移值存储在由校准控制电路（40）控制的偏移寄存器（26）中。 Δ-Σ调制器（16）的输出被输入到由模拟滤波器（22）和输出放大器（28）组成的模拟部分（12）。输出放大器（28）可操作以对模拟滤波器（22）的输出进行采样并将其馈送到门（38）。门（38）在校准周期期间被激活，以将比较器输出反馈给校准控制电路（40）。在校准周期期间，输出由隔离放大器（32）隔离，模拟输出焊盘通过开关（44）连接到地，以在模拟输出端提供低阻抗输出。校准控制电路（40）可操作用于对强制为逻辑低的内插电路（14）的输入对模拟部分（12）的输出进行采样，执行二进制搜索。

78. 发明授权

US4550284A MOS Cascode current mirror 失效
标题翻译： MOS Cascode电流镜
公开(公告)号：US4550284A
公开(公告)日：1985-10-29
申请号：US610881
申请日：1984-05-16
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03F3/343 , G05F3/26 , H01L29/78 , H03F3/34 , H03F3/345 , G05F3/08
CPC分类号： G05F3/262
摘要： An MOS current mirror is disclosed which comprises only two circuit branches and requires only a single reference current. The input circuit branch includes at least four MOS transistors (40, 42, 44, 46) connected in series and the output circuit branch includes at least two MOS transistors (48, 50) interconnected with selected transistors of the input circuit branch. Mirroring of the input current (I.sub.REF) is accomplished by providing a transistor (46, 50) in each circuit branch with identical operating characteristics (V.sub.DS, V.sub.GS). High output impedance is achieved in accordance with the present invention by adjusting the channel constant (Z/L) of another transistor (42) in the input circuit branch to be one-third the value of the channel constant associated with each of the remaining transistors.
摘要翻译：公开了仅包括两个电路分支并且仅需要单个参考电流的MOS电流镜。输入电路支路包括串联连接的至少四个MOS晶体管（40,42,44,46），并且输出电路支路包括与输入电路支路的选定晶体管互连的至少两个MOS晶体管（48,50）。通过在每个电路支路中提供具有相同工作特性（VDS，VGS）的晶体管（46,50）来实现输入电流（IREF）的镜像。根据本发明，通过调节输入电路支路中另一个晶体管（42）的通道常数（Z / L）达到与每个剩余晶体管相关的沟道常数值的三分之一来实现高输出阻抗。

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