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71. 发明申请

US20100304555A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100304555A1
公开(公告)日：2010-12-02
申请号：US12805533
申请日：2010-08-04
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译：本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力，在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

72. 发明授权

US07772076B2 Method of manufacturing semiconductor device using dummy gate wiring layer 失效
标题翻译：使用伪栅极布线层制造半导体器件的方法
公开(公告)号：US07772076B2
公开(公告)日：2010-08-10
申请号：US11715965
申请日：2007-03-09
申请人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
发明人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L21/336
CPC分类号： H01L29/66575 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104 , H01L29/1033 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/78 , Y10S438/926
摘要： A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area, thereafter, forming a semiconductor film on the second area of the major surface of the substrate by using epitaxial growth, the semiconductor film having a thickness smaller than a thickness of the dummy gate wiring layer, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers the side surface of the dummy gate wiring layer.
摘要翻译：一种制造半导体器件的方法包括在衬底的一个主表面的第一区域上形成具有侧表面和上表面的虚拟栅极布线层，所述衬底的主表面包括第一区域和第二区域，之后通过使用外延生长在所述衬底的主表面的第二区域上形成半导体膜，所述半导体膜的厚度小于所述虚拟栅极布线层的厚度，并且在所述半导体膜上形成栅极侧壁，所述栅极侧壁由绝缘体制成并覆盖虚拟栅极布线层的侧表面。

73. 发明申请

US20070290223A1 Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070290223A1
公开(公告)日：2007-12-20
申请号：US11802852
申请日：2007-05-25
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L33/00
CPC分类号： H01L29/0847 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/785 , H01L29/7923
摘要： A semiconductor memory device includes an insulating film formed on a semiconductor substrate, a fin-shaped semiconductor layer formed on the insulating film, and having first and second side surfaces opposing each other, a gate electrode formed across the first side surface and second side surface of the semiconductor layer, a trap layer formed between the gate electrode and the first side surface of the semiconductor layer, a tunnel gate insulating film formed between the trap layer and the first and second side surfaces of the semiconductor layer, a block layer formed between the trap layer and the gate electrode, a channel region formed in the semiconductor layer below the gate electrode, and a source and drain regions formed in the semiconductor layer to sandwich the channel region and containing a metal, a Schottky junction being formed between the channel region and each of the source and drain regions.
摘要翻译：半导体存储器件包括形成在半导体衬底上的绝缘膜，形成在绝缘膜上的鳍状半导体层，并且具有彼此相对的第一和第二侧表面;跨越第一侧表面和第二侧表面形成的栅电极形成在所述半导体层的所述栅电极和所述第一侧表面之间的陷阱层，形成在所述阱层与所述半导体层的所述第一和第二侧表面之间的隧道栅极绝缘膜，陷阱层和栅电极，形成在栅电极下方的半导体层中的沟道区，以及形成在半导体层中以夹持沟道区并包含金属的源极和漏极区，形成在沟道之间的肖特基结区域和源极和漏极区域中的每一个。

74. 发明申请

US20070190708A1 Semiconductor device and method manufacturing semiconductor device 有权
标题翻译：半导体器件和方法制造半导体器件
公开(公告)号：US20070190708A1
公开(公告)日：2007-08-16
申请号：US11700147
申请日：2007-01-31
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译：本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力，在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

75. 发明授权

US07247913B2 Semiconductor device having a Schottky source/drain transistor 失效
标题翻译：具有肖特基源极/漏极晶体管的半导体器件
公开(公告)号：US07247913B2
公开(公告)日：2007-07-24
申请号：US11116328
申请日：2005-04-28
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/458 , H01L29/785 , H01L29/78618
摘要： A semiconductor device comprises an island shaped channel layer formed on a substrate, the channel later being composed of a semiconductor material, a gate insulation film formed on the channel layer, a gate electrode formed on the gate insulation film, an insulation film formed on both side faces opposite to one direction of the channel layer, a source electrode and a drain electrode made of a metal material and formed on a side face of the insulation layer.
摘要翻译：半导体器件包括形成在衬底上的岛状沟道层，该沟道稍后由半导体材料构成，形成在沟道层上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在二极管上的绝缘膜与沟道层的一个方向相反的侧面，由金属材料制成并形成在绝缘层的侧面上的源电极和漏电极。

76. 发明授权

US07208797B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07208797B2
公开(公告)日：2007-04-24
申请号：US10023849
申请日：2001-12-21
申请人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
发明人： Atsushi Yagishita , Kouji Matsuo , Yasushi Akasaka , Kyoichi Suguro , Yoshitaka Tsunashima
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/66575 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104 , H01L29/1033 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/78 , Y10S438/926
摘要： There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.
摘要翻译：提供了一种半导体器件，包括衬底，在衬底上形成的器件隔离绝缘膜，形成在衬底上的栅电极，形成在器件隔离绝缘膜中并连接到栅电极的栅极布线层，源极和漏极布置在基板上，经由栅极电极相对对置;以及绝缘膜，其覆盖栅极电极和栅极布线层中的每一个的底部和侧面，其中栅极，源极和漏极以及栅极布线层具有上表面水平等于或低于器件绝缘膜的绝缘膜。

77. 发明申请

US20070004117A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070004117A1
公开(公告)日：2007-01-04
申请号：US11451318
申请日：2006-06-13
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other.
摘要翻译：制造半导体器件的方法包括在绝缘层上形成包括半导体材料的多个金属丝; 在金属丝的侧壁上形成栅极绝缘膜; 形成栅极电极，所述栅电极在所述鳍片的布置方向上延伸并且与所述鳍状物电绝缘，所述栅极电极在所述栅极绝缘膜上的所述鳍片中是共同的; 通过使用栅电极作为掩模将杂质注入到薄片的部分中以形成源 - 漏扩散层，所述鳍的部分在栅电极的两侧延伸; 以及在所述金属丝的两侧上沉积导电材料以将所述金属丝彼此连接。

78. 发明申请

US20060275988A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060275988A1
公开(公告)日：2006-12-07
申请号：US11404772
申请日：2006-04-17
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译：根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

79. 发明申请

US20050202618A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050202618A1
公开(公告)日：2005-09-15
申请号：US11058190
申请日：2005-02-16
申请人： Atsushi Yagishita
发明人： Atsushi Yagishita
IPC分类号： H01L29/786 , H01L21/20 , H01L21/336 , H01L21/84 , H01L29/423 , H01L29/78
CPC分类号： H01L29/785 , H01L21/84 , H01L29/42384 , H01L29/665 , H01L29/66795
摘要： A manufacturing method of a semiconductor device disclosed herein comprises: forming a convex first protrusion; forming a first film, of which a surface is higher than the first protrusion; forming a mask portion on the first film; and etching the first film with the mask portion as a mask.
摘要翻译：本文公开的半导体器件的制造方法包括：形成凸起的第一突起; 形成第一膜，其表面高于第一突起; 在所述第一膜上形成掩模部分; 并用掩模部分作为掩模蚀刻第一膜。

80. 发明授权

US06919260B1 Method of manufacturing a substrate having shallow trench isolation 失效
标题翻译：制造具有浅沟槽隔离的衬底的方法
公开(公告)号：US06919260B1
公开(公告)日：2005-07-19
申请号：US09358388
申请日：1999-07-21
申请人： Kaori Umezawa , Norihiko Tsuchiya , Yoshiaki Matsushita , Hiroyuki Kamijou , Atsushi Yagishita , Tsunehiro Kita
发明人： Kaori Umezawa , Norihiko Tsuchiya , Yoshiaki Matsushita , Hiroyuki Kamijou , Atsushi Yagishita , Tsunehiro Kita
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/76232 , H01L21/76275 , H01L21/76283
摘要： A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350° C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.
摘要翻译：提供具有浅沟槽隔离（STI）结构的半导体衬底及其制造方法，即，在半导体衬底的预定位置选择性地形成沟槽并且使用有机硅源作为材料的氧化物膜的隔离衬底埋在凹槽中作为掩埋氧化膜。本发明的特征在于，在半导体衬底的平坦化之前或之后，在1100至1350℃的范围内的预定温度下对所述掩埋氧化物膜进行退火，使得环状结构多于5倍的环和环结构在掩埋氧化膜中以预定的速率形成小于4倍的环。通过上述退火，能够缓和埋入槽内的氧化膜的应力。因此，错位的产生被抑制。

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