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71. 发明授权

US07727900B2 Surface preparation for gate oxide formation that avoids chemical oxide formation 有权
标题翻译：防止化学氧化物形成的栅极氧化物形成的表面处理
公开(公告)号：US07727900B2
公开(公告)日：2010-06-01
申请号：US11358624
申请日：2006-02-21
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Shih-Chang Chen
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31111 , H01L21/0206 , H01L21/28167 , H01L21/31133 , H01L21/823462
摘要： A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.
摘要翻译：可用于半导体制造的清洁顺序有效地清洁半导体衬底，同时防止其上形成化学氧化物。该序列包括以下顺序：1）用HF溶液处理; 2）用纯H 2 SO 4处理; 3）用H 2 O 2溶液处理; 4）去离子水冲洗; 和5）用HCl溶液处理。纯H 2 SO 4溶液可以包括约百分之九十八（98％）或更高的H 2 SO 4浓度。在HCl溶液处理之后，清洁的表面可以是不含厚度为5埃或更大的化学氧化物的硅表面。本发明在利用多个栅极氧化物厚度的半导体器件中具有特别的优点。

72. 发明授权

US07713854B2 Gate dielectric layers and methods of fabricating gate dielectric layers 有权
标题翻译：栅极电介质层和制造栅极电介质层的方法
公开(公告)号：US07713854B2
公开(公告)日：2010-05-11
申请号：US11551577
申请日：2006-10-20
申请人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
发明人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/31155 , H01L21/02126 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/26506 , H01L21/28185 , H01L21/2822 , H01L21/3141 , H01L21/31633 , H01L21/31662 , H01L21/823462
摘要： A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.
摘要翻译：形成栅极电介质层的方法包括在衬底上形成栅极电介质层。用含碳离子处理栅介质层。栅极电介质层被热处理，从而为栅极电介质层提供约1原子％至约20原子％之间的碳含量。

73. 发明申请

US20090287652A1 DISTRIBUTED AUDIO VISUAL SYSTEM AND CONTENT DIRECTORY MANAGEMENT SYSTEM AND METHOD THEREOF 有权
标题翻译：分布式音频视觉系统和内容目录管理系统及其方法
公开(公告)号：US20090287652A1
公开(公告)日：2009-11-19
申请号：US12337592
申请日：2008-12-17
申请人： Chi-Chun Chen , Jian-Hong Liu , Yi-Chang Zhuang
发明人： Chi-Chun Chen , Jian-Hong Liu , Yi-Chang Zhuang
IPC分类号： G06F17/30
CPC分类号： H04L12/2812 , H04L65/4084 , H04L67/104 , H04L67/1063 , H04L67/1095 , H04L2012/2849 , H04N7/165 , H04N21/2665 , H04N21/278
摘要： A distributed audio visual (AV) system including a plurality of media servers, a media renderer, and a control point which are connected to each other via a peer-to-peer network is provided. Each of the media servers includes a content directory management unit (CDMU) and a query content information (QCI) module, wherein the CDMU includes a synchronizer module and a content information maintainer (CIM) module. The synchronizer module synchronizes content information of AV contents stored in all the media servers. The CIM module records the content information and establishes an integrated content directory list according to the content information. The QCI module queries the content information. The control point obtains the integrated content directory list from one of the media servers and queries the content information related to all the AV contents, so as to control the media renderer to play the AV contents.
摘要翻译：提供了包括经由点对点网络彼此连接的多个媒体服务器，媒体渲染器和控制点的分布式视听（AV）系统。每个媒体服务器包括内容目录管理单元（CDMU）和查询内容信息（QCI）模块，其中CDMU包括同步器模块和内容信息维护器（CIM）模块。同步器模块同步所有媒体服务器中存储的AV内容的内容信息。 CIM模块记录内容信息，并根据内容信息建立综合内容目录列表。 QCI模块查询内容信息。控制点从媒体服务器之一获取综合内容目录列表，查询与所有AV内容有关的内容信息，以控制媒体渲染器播放AV内容。

74. 发明授权

US07544561B2 Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation 有权
标题翻译：具有氮化多晶硅再氧化的MOS器件的电子迁移率增强
公开(公告)号：US07544561B2
公开(公告)日：2009-06-09
申请号：US11593293
申请日：2006-11-06
申请人： Wenli Lin , Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
发明人： Wenli Lin , Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/28247 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate dielectric, and a first gate spacer along sidewalls of the first gate electrode and the first gate dielectric. The NMOS device includes a second gate dielectric on the semiconductor substrate, a second gate electrode on the second gate dielectric, a nitrided polysilicon re-oxidation layer having a vertical portion and a horizontal portion wherein the vertical portion is on sidewalls of the second gate electrode and the second gate dielectric and wherein the horizontal portion is on the semiconductor substrate, and a second gate spacer on sidewalls of the second gate electrode and the second gate dielectric, wherein the second gate spacer is on the horizontal portion of the nitrided polysilicon re-oxidation layer.
摘要翻译：半导体结构包括PMOS器件和NMOS器件。 PMOS器件包括半导体衬底上的第一栅极电介质，第一栅极电介质上的第一栅极电极和沿着第一栅极电极和第一栅极电介质的侧壁的第一栅极间隔物。所述NMOS器件包括在所述半导体衬底上的第二栅极电介质，所述第二栅极电介质上的第二栅极电极，具有垂直部分和水平部分的氮化多晶硅再氧化层，其中所述垂直部分位于所述第二栅电极的侧壁上和所述第二栅极电介质，并且其中所述水平部分在所述半导体衬底上，以及在所述第二栅极电极和所述第二栅极电介质的侧壁上的第二栅极间隔物，其中所述第二栅极间隔物位于所述氮化多晶硅的水平部分上，氧化层。

75. 发明申请

US20090043936A1 DOCKING STATION AND EXPANDABLE COMPUTER SYSTEM 审中-公开
标题翻译：锁定站和可扩展计算机系统
公开(公告)号：US20090043936A1
公开(公告)日：2009-02-12
申请号：US12138974
申请日：2008-06-13
申请人： Cheng-Hung YANG , Kuei-Kang Chang , Chi-Chun Chen , Wan-Shan Lin , Wen-Chi Kuo
发明人： Cheng-Hung YANG , Kuei-Kang Chang , Chi-Chun Chen , Wan-Shan Lin , Wen-Chi Kuo
IPC分类号： G06F13/00
CPC分类号： G06F1/1632
摘要： A docking station is used for cooperating with a computer host, and the computer host has a first power connecting portion and a first peripheral component connecting portion. The docking station includes a casing, a second power connecting portion and a second peripheral component connecting portion. The casing is used for disposing the computer host. The second power connecting portion and the second peripheral component connecting portion are disposed at the casing. When the computer host is disposed at the casing, the second power connecting portion is connected to the first power connecting portion to transmit a power signal to the computer host, and the second peripheral component connecting portion is connected to the first peripheral component connecting portion to transmit at least one peripheral component signal to the computer host. An expandable computer system is also disclosed.
摘要翻译：对接站用于与计算机主机协作，计算机主机具有第一电源连接部分和第一外围部件连接部分。对接站包括壳体，第二电力连接部分和第二外围部件连接部分。外壳用于处理计算机主机。第二电源连接部分和第二外围部件连接部分设置在壳体上。当计算机主机设置在壳体上时，第二电源连接部分连接到第一电力连接部分以将电力信号传送到计算机主机，并且第二外围部件连接部分连接到第一外围部件连接部分向计算机主机发送至少一个外围组件信号。还公开了可扩展计算机系统。

76. 发明申请

US20080230814A1 Methods for fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080230814A1
公开(公告)日：2008-09-25
申请号：US11725453
申请日：2007-03-20
申请人： Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
发明人： Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28202 , H01L21/823462 , H01L27/088 , H01L29/518 , H01L29/78
摘要： A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH3-plasma, having a nitrogen-concentration of about 1013˜1021 atoms/cm2 therein.
摘要翻译：一种制造半导体器件的方法包括提供含有第一，第二和第三区域的含硅衬底。第一，第二和第三栅极堆叠分别覆盖在第一，第二和第三区域中的含硅衬底的一部分。间隔件形成在第一，第二和第三栅极堆叠中的每一个的相对侧壁上，间隔物分别在第一，第二和第三区域中的含硅衬底的一部分上方覆盖。源/漏区形成在第一，第二和第三区域中的含硅衬底的一部分中，源/漏区分别与第一，第二和第三栅堆叠相邻。第一，第二和第三栅极堆叠具有各种厚度的第一，第二和第三栅极电介质层，并且具有相对薄的厚度的至少一个栅极电介质层通过NH 3 - 等离子体处理，具有氮 - 其中约10 13〜20个/ cm 2的浓度。

77. 发明授权

US07271450B2 Dual-gate structure and method of fabricating integrated circuits having dual-gate structures 有权
标题翻译：双栅极结构和制造具有双栅极结构的集成电路的方法
公开(公告)号：US07271450B2
公开(公告)日：2007-09-18
申请号：US11303530
申请日：2005-12-16
申请人： Tuo-Hung Ho , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Chih-Chang Chen
发明人： Tuo-Hung Ho , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Chih-Chang Chen
IPC分类号： H01L29/94
CPC分类号： H01L21/823462 , H01L21/31111 , H01L29/513 , H01L29/517
摘要： A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
摘要翻译：提供了一种在衬底上制造双栅极的方法和具有双栅极结构的集成电路。第一高K电介质层形成在为第一栅极结构限定的第一区域和在为第二栅极结构限定的第二区域中。在第一和第二区域中形成第二高K电介质层。第一高K电介质层相对于第二高K电介质层具有比腐蚀剂更低的蚀刻速率。使用蚀刻剂将第二高K电介质层从第二区域蚀刻到所述第一高K电介质层，并且在第二高K电介质层上的第一和第二区域中形成栅极导电层， K电介质层。

78. 发明申请

US20060091469A1 Dual-gate structure and method of fabricating integrated circuits having dual-gate structures 有权
标题翻译：双栅极结构和制造具有双栅极结构的集成电路的方法
公开(公告)号：US20060091469A1
公开(公告)日：2006-05-04
申请号：US11303530
申请日：2005-12-16
申请人： Tuo-Hung Ho , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Chih-Chang Chen
发明人： Tuo-Hung Ho , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Chih-Chang Chen
IPC分类号： H01L29/94
CPC分类号： H01L21/823462 , H01L21/31111 , H01L29/513 , H01L29/517
摘要： A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
摘要翻译：提供了一种在衬底上制造双栅极的方法和具有双栅极结构的集成电路。第一高K电介质层形成在为第一栅极结构限定的第一区域和在为第二栅极结构限定的第二区域中。在第一和第二区域中形成第二高K电介质层。第一高K电介质层相对于第二高K电介质层具有比腐蚀剂更低的蚀刻速率。使用蚀刻剂将第二高K电介质层从第二区域蚀刻到所述第一高K电介质层，并且在第二高K电介质层上的第一和第二区域中形成栅极导电层， K电介质层。

79. 发明授权

US07030024B2 Dual-gate structure and method of fabricating integrated circuits having dual-gate structures 失效
公开(公告)号：US07030024B2
公开(公告)日：2006-04-18
申请号：US10226617
申请日：2002-08-23
申请人： Tuo-Hung Ho , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Chih-Chang Chen
发明人： Tuo-Hung Ho , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Chih-Chang Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/823462 , H01L21/31111 , H01L29/513 , H01L29/517
摘要： A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

80. 发明授权

US06890811B2 Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices 有权
标题翻译：双栅电介质方案：用于高性能器件的SiON和低功率器件的高k
公开(公告)号：US06890811B2
公开(公告)日：2005-05-10
申请号：US10679768
申请日：2003-10-06
申请人： Tou-Hung Hou , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Shih-Chang Chen
发明人： Tou-Hung Hou , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/8234 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/823456 , H01L21/823462
摘要： A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT
摘要翻译：描述了可扩展以满足对于50nm和70nm技术节点的要求的形成双栅极电介质层的方法。衬底具有分离器件区域的STI区域。界面层和高k电介质层依次沉积在衬底上。在一个器件区域上去除两个层，并且在暴露的器件区域上生长具有EOT <10nm的超薄氮氧化硅层。在SiON介电层的生长期间，高k电介质层退火。高k电介质层由金属氧化物或其硅酸盐或铝酸盐形成，并且能够以具有抑制的漏电流的EOT <1.8nm制造低功率器件。当形成多个栅极时，该方法与双重或三重氧化物厚度工艺兼容。

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