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71. 发明授权

US5974070A II-VI laser diode with facet degradation reduction structure 失效
标题翻译：具有小面降解结构的II-VI激光二极管
公开(公告)号：US5974070A
公开(公告)日：1999-10-26
申请号：US972025
申请日：1997-11-17
申请人： Michael A. Haase , Paul Frederic Baude
发明人： Michael A. Haase , Paul Frederic Baude
IPC分类号： H01S5/10 , H01S5/026 , H01S5/028 , H01S5/042 , H01S5/0625 , H01S5/16 , H01S5/323 , H01S5/347 , H01S3/19
CPC分类号： B82Y20/00 , H01S5/16 , H01S5/347 , H01S5/0264 , H01S5/028 , H01S5/0425 , H01S5/0625
摘要： A II-VI semiconductor laser diode having a semiconductor body comprising a plurality of semiconductor layers forming a pn junction, a facet at one end of the body, and a reference electrode. The laser diode further includes a facet degradation reduction electrode located adjacent to the facet. The facet degradation reduction electrode is electrically isolated from a forward bias electrode. The facet degradation reduction electrode is used to establish an electric field sufficient to reduce facet degradation. In one embodiment, this electric field is established by applying a reverse-bias voltage between the facet electrode and the reference electrode. In another embodiment, this electric field is established by electrically connecting the facet electrode to the reference electrode.
摘要翻译：具有半导体主体的II-VI半导体激光二极管，该半导体主体包括形成pn结的多个半导体层，在主体一端的小面和参考电极。激光二极管还包括邻近小面定位的小面降解还原电极。小面降解还原电极与正向偏置电极电隔离。小面降解还原电极用于建立足以减少小面降解的电场。在一个实施例中，通过在小面电极和参考电极之间施加反向偏置电压来建立该电场。在另一实施例中，通过将小面电极与参考电极电连接来建立该电场。

72. 发明授权

US5395791A Growth of II VI laser diodes with quantum wells by atomic layer epitaxy and migration enhanced epitaxy 失效
标题翻译：通过原子层外延和迁移强化外延生长具有量子阱的II VI激光二极管
公开(公告)号：US5395791A
公开(公告)日：1995-03-07
申请号：US139614
申请日：1993-10-20
申请人： Hwa Cheng , James M. DePuydt , Michael A. Haase , Jun Qiu
发明人： Hwa Cheng , James M. DePuydt , Michael A. Haase , Jun Qiu
IPC分类号： H01S5/00 , H01L21/363 , H01L33/00 , H01S5/34 , H01S5/347 , H01L21/203
CPC分类号： H01S5/347 , B82Y20/00 , H01L21/02395 , H01L21/02474 , H01L21/02477 , H01L21/0248 , H01L21/02491 , H01L21/02507 , H01L21/02557 , H01L21/0256 , H01L21/02562 , H01L21/02576 , H01L21/02579 , H01L21/02631 , H01L2924/0002 , H01L33/0087 , H01S5/3403 , H01S5/3406 , H01S5/342
摘要： A method for using atomic layer epitaxy (ALE) and/or migration enhanced epitaxy (MEE) to grow high efficiency quantum wells in II-VI laser diodes. The substrate and previously grown layers of the laser diode are heated to a temperature less than or equal to about 200.degree. C. in an MBE chamber. Sources of Cd, Zn, and Se are injected alternately into the chamber to grow a short-period strained-layer superlattice (SPSLS) quantum well layer including overlaying monolayers of Cd, Zn and Se. The quantum well layer is described by the notation [(CdSe).sub.m (ZnSe).sub.n ].sub.p where m, n and p are integers.
摘要翻译：使用原子层外延（ALE）和/或迁移增强外延（MEE）来生长II-VI激光二极管中的高效量子阱的方法。激光二极管的衬底和先前生长的层在MBE室中被加热到小于或等于约200℃的温度。将Cd，Zn和Se的来源交替注入室内，以生长包括Cd，Zn和Se的单层的短周期应变层超晶格（SPSLS）量子阱层。量子阱层由符号[（CdSe）m（ZnSe）n] p描述，其中m，n和p是整数。

73. 发明授权

US4301509A Method for cooking meat or poultry in thermal oven 失效
标题翻译：在烤箱中烹制肉类或家禽的方法
公开(公告)号：US4301509A
公开(公告)日：1981-11-17
申请号：US93685
申请日：1979-11-13
申请人： Michael A. Haase , Edward B. Miller , Charles W. Eichelberger , Scott E. Cutler , Robert J. Wojnarowski
发明人： Michael A. Haase , Edward B. Miller , Charles W. Eichelberger , Scott E. Cutler , Robert J. Wojnarowski
IPC分类号： F24C7/00 , G06F15/20 , H05B1/02
CPC分类号： F24C7/006 , F24C7/085
摘要： Meat or poultry is cooked automatically in a thermal oven to a desired degree of doneness by a chosen time. The temperature of the meat or poultry is monitored, and linear extrapolations are made therefrom. These extrapolations are compared to the course the cooking should follow, and the oven temperature is automatically varied to correct deviations from the ideal course.
摘要翻译：肉或家禽在热烘箱中自动烹饪至所需时间的期望程度。监测肉类或家禽的温度，并由此进行线性外推。将这些外推与烹饪应遵循的过程进行比较，并且烘箱温度自动变化，以纠正与理想过程的偏差。

74. 发明授权

US08826528B2 Electrical connections for anodized thin film structures 有权
标题翻译：阳极氧化薄膜结构的电气连接
公开(公告)号：US08826528B2
公开(公告)日：2014-09-09
申请号：US13131740
申请日：2009-12-03
申请人： Steven D. Theiss , Michael A. Haase
发明人： Steven D. Theiss , Michael A. Haase
IPC分类号： H05K3/00 , H01L21/768 , H05K3/40 , H01L27/12
CPC分类号： H01L21/76802 , H01L27/1214 , H01L27/124 , H01L2224/24137 , H05K3/4092 , Y10T29/49002 , Y10T29/49124 , Y10T29/49147 , Y10T428/12396
摘要： Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier. The second metallization layer is disposed over the anodized layer, making electrical contact with the first electrically conductive layer in the via connection region.
摘要翻译：描述了形成电路的方法，通过该电路将第一薄膜金属化层电连接到第二薄膜金属化层。通孔形成涉及在阳极氧化第一金属化层之前使用设置在通孔连接区域中的阳极氧化屏障和/或补充焊盘。用于形成屏障的材料在阳极氧化期间对于阳极氧化溶液是基本上不可渗透的，并且破坏导电层和阻挡层之间的氧化物的形成。辅助垫是非阳极氧化的，并被屏障覆盖，以在阳极氧化期间基本上防止电流流过垫。阳极氧化后，屏障被去除。如果补充垫具有足够的导电性，则可以在去除屏障之后留在第一金属化层上。第二金属化层设置在阳极氧化层上，与通孔连接区域中的第一导电层电接触。

75. 发明授权

US08765611B2 Etching process for semiconductors 失效
标题翻译：半导体蚀刻工艺
公开(公告)号：US08765611B2
公开(公告)日：2014-07-01
申请号：US12917826
申请日：2010-11-02
申请人： Michael A. Haase , Terry L. Smith , Jun-Ying Zhang
发明人： Michael A. Haase , Terry L. Smith , Jun-Ying Zhang
IPC分类号： H01L21/027
CPC分类号： H01L31/02363 , H01L21/465 , H01L33/0095 , H01L33/22 , H01L2933/0083 , Y02E10/50
摘要： A process for etching semiconductors, such as II-VI or III-V semiconductors is provided. The method includes sputter etching the semiconductor through an etching mask using a nonreactive gas, removing the semiconductor and cleaning the chamber with a reactive gas. The etching mask includes a photoresist. Using this method, light-emitting diodes with light extracting elements or nano/micro-structures etched into the semiconductor material can be fabricated.
摘要翻译：提供了蚀刻半导体的方法，例如II-VI或III-V半导体。该方法包括通过使用非反应性气体的蚀刻掩模溅射半导体蚀刻，去除半导体并用反应气体清洁室。蚀刻掩模包括光致抗蚀剂。使用这种方法，可以制造具有光提取元件的发光二极管或蚀刻到半导体材料中的纳米/微结构。

76. 发明授权

US08318552B2 Method for forming gate structures 有权
标题翻译：形成栅极结构的方法
公开(公告)号：US08318552B2
公开(公告)日：2012-11-27
申请号：US12665094
申请日：2008-05-20
申请人： Jeffrey H. Tokie , Michael A. Haase , Robert J. Schubert , Michael W. Bench , Donald J. McClure , Grace L. Ho
发明人： Jeffrey H. Tokie , Michael A. Haase , Robert J. Schubert , Michael W. Bench , Donald J. McClure , Grace L. Ho
IPC分类号： H01L21/677 , H01L27/12 , H01L29/49 , H01L29/786
CPC分类号： H01L27/124 , H01L21/6776 , H01L27/1225 , H01L29/4908 , H01L29/7869
摘要： A process for forming gate structures is described. A web comprises a substrate, a plurality of conductive elements disposed on the substrate, and a conductive anodization bus. The web is moved through an anodization station to form a plurality of gate structures comprising a plurality of gate dielectrics adjacent to a plurality of gate electrodes. A process for forming electronic devices further providing a semiconductor, a source electrode, and a drain electrode is described.
摘要翻译：描述了用于形成栅极结构的工艺。网状物包括衬底，设置在衬底上的多个导电元件和导电阳极氧化母线。幅材移动通过阳极氧化站以形成包括与多个栅电极相邻的多个栅极电介质的多个栅极结构。描述了进一步提供半导体，源电极和漏电极的电子器件的形成工艺。

77. 发明申请

US20110242778A1 Electrical Connections for Anodized Thin Film Structures 有权
标题翻译：阳极氧化薄膜结构的电气连接
公开(公告)号：US20110242778A1
公开(公告)日：2011-10-06
申请号：US13131740
申请日：2009-12-03
申请人： Steven D. Theiss , Michael A. Haase
发明人： Steven D. Theiss , Michael A. Haase
IPC分类号： H05K7/00 , C25D5/02 , C25D7/00 , H05K3/07 , B32B3/10
CPC分类号： H01L21/76802 , H01L27/1214 , H01L27/124 , H01L2224/24137 , H05K3/4092 , Y10T29/49002 , Y10T29/49124 , Y10T29/49147 , Y10T428/12396
摘要： Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier. The second metallization layer is disposed over the anodized layer, making electrical contact with the first electrically conductive layer in the via connection region.
摘要翻译：描述了形成电路的方法，通过该电路将第一薄膜金属化层电连接到第二薄膜金属化层。通孔形成涉及在阳极氧化第一金属化层之前使用设置在通孔连接区域中的阳极氧化屏障和/或补充焊盘。用于形成屏障的材料在阳极氧化期间对于阳极氧化溶液是基本上不可渗透的，并且破坏导电层和阻挡层之间的氧化物的形成。辅助垫是非阳极氧化的，并被屏障覆盖，以在阳极氧化期间基本上防止电流流过垫。阳极氧化后，屏障被去除。如果补充垫具有足够的导电性，则可以在去除屏障之后留在第一金属化层上。第二金属化层设置在阳极氧化层上，与通孔连接区域中的第一导电层电接触。

78. 发明申请

US20110101402A1 SEMICONDUCTOR LIGHT CONVERTING CONSTRUCTION 审中-公开
标题翻译：半导体光转换结构
公开(公告)号：US20110101402A1
公开(公告)日：2011-05-05
申请号：US13000592
申请日：2009-06-10
申请人： Jun-Ying Zhang , Terry L. Smith , Michael A. Haase
发明人： Jun-Ying Zhang , Terry L. Smith , Michael A. Haase
IPC分类号： H01L33/00
CPC分类号： H01L33/50 , H01L33/08 , H01L33/44 , H01L2933/0091
摘要： Semiconductor light converting constructions are disclosed. The semiconductor light converting construction includes a semiconductor potential well for converting at least a portion of light at a first wavelength to light at a longer second wavelength; an outer layer that is disposed on the semiconductor potential well and has a first index of refraction; and a structured layer that is disposed on the outer layer and has a second index of refraction that is smaller than the first index of refraction. The structured layer includes a plurality of structures that are disposed directly on the outer layer and a plurality of openings that expose the outer layer. The semiconductor light converting construction further includes a structured overcoat that is disposed directly on at least a portion of the structured layer and a portion of the outer layer in the plurality of openings. The overcoat has a third index of refraction that is greater than the second index of refraction.
摘要翻译：公开了半导体光转换结构。半导体光转换结构包括用于将第一波长的至少一部分光转换成较长第二波长的光的半导体势阱; 外层，其设置在所述半导体势阱上并具有第一折射率; 以及设置在外层上并且具有小于第一折射率的第二折射率的结构化层。结构化层包括直接设置在外层上的多个结构和暴露外层的多个开口。半导体光转换结构还包括直接设置在结构化层的至少一部分上的多个开口中的外层的一部分的结构化外涂层。外涂层具有大于第二折射率的第三折射率。

79. 发明授权

US07863634B2 LED device with re-emitting semiconductor construction and reflector 有权
标题翻译： LED器件具有重新发射半导体结构和反射器
公开(公告)号：US07863634B2
公开(公告)日：2011-01-04
申请号：US11761148
申请日：2007-06-11
申请人： Michael A. Haase
发明人： Michael A. Haase
IPC分类号： H01L29/22
CPC分类号： H01L33/08 , H01L33/505 , H01L2224/48091 , H01L2224/48247 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： Briefly, the present disclosure provides a device comprising: a) an LED capable of emitting light at a first wavelength; b) a re-emitting semiconductor construction which comprises a potential well not located within a pn junction; and c) a reflector positioned to reflect light emitted from the LED onto the re-emitting semiconductor construction. Alternately, the device comprises: a) an LED capable of emitting light at a first wavelength; b) a re-emitting semiconductor construction capable of emitting light at a second wavelength which comprises at least one potential well not located within a pn junction; and c) a reflector which transmits light at said first wavelength and reflects at least a portion of light at said second wavelength. Alternately, the device comprises a semiconductor unit comprising a first potential well located within a pn junction which comprises a LED capable of emitting light at a first wavelength, and a second potential well not located within a pn junction which comprises a re-emitting semiconductor construction.
摘要翻译：简而言之，本公开提供了一种装置，包括：a）能够发射第一波长的光的LED; b）再发射半导体结构，其包括不位于pn结内的势阱; 以及c）反射器，其被定位成将从LED发射的光反射到再发射半导体结构上。或者，该装置包括：a）能够发射第一波长的光的LED; b）能够发射第二波长的光的再发射半导体结构，其包括不位于pn结内的至少一个势阱; 以及c）透射所述第一波长的光并反射所述第二波长的至少一部分光的反射器。或者，该装置包括半导体单元，该半导体单元包括位于pn结内的第一势阱，该第一势阱包括能够发射第一波长的光的LED和不位于pn结内的第二势阱，该第二势阱包括再发射半导体结构。

80. 发明申请

US20100252176A1 METHOD FOR FORMING GATE STRUCTURES 有权
标题翻译：形成门结构的方法
公开(公告)号：US20100252176A1
公开(公告)日：2010-10-07
申请号：US12665094
申请日：2008-05-20
申请人： Jeffrey H. Tokie , Michael A. Haase , Robert J. Schubert , Michael W. Bench , Donald J. McClure , Grace L. Ho
发明人： Jeffrey H. Tokie , Michael A. Haase , Robert J. Schubert , Michael W. Bench , Donald J. McClure , Grace L. Ho
IPC分类号： C25D7/00 , C25D11/02
CPC分类号： H01L27/124 , H01L21/6776 , H01L27/1225 , H01L29/4908 , H01L29/7869
摘要： A process for forming gate structures is described. A web comprises a substrate, a plurality of conductive elements disposed on the substrate, and a conductive anodization bus. The web is moved through an anodization station to form a plurality of gate structures comprising a plurality of gate dielectrics adjacent to a plurality of gate electrodes. A process for forming electronic devices further providing a semiconductor, a source electrode, and a drain electrode is described.
摘要翻译：描述了用于形成栅极结构的工艺。网状物包括衬底，设置在衬底上的多个导电元件和导电阳极氧化母线。幅材移动通过阳极氧化站以形成包括与多个栅电极相邻的多个栅极电介质的多个栅极结构。描述了进一步提供半导体，源电极和漏电极的电子器件的形成工艺。

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