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71. 发明申请

US20080290379A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20080290379A1
公开(公告)日：2008-11-27
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234 , H01L29/04
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

72. 发明授权

US07453123B2 Self-aligned planar double-gate transistor structure 有权
标题翻译：自对平面双栅晶体管结构
公开(公告)号：US07453123B2
公开(公告)日：2008-11-18
申请号：US11676030
申请日：2007-02-16
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , Meikei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , Meikei Ieong , Erin Catherine Jones
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

73. 发明授权

US07425483B2 Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices 有权
标题翻译：制造用于高性能混合取向硅绝缘体上CMOS器件的混合衬底的结构和方法
公开(公告)号：US07425483B2
公开(公告)日：2008-09-16
申请号：US11830489
申请日：2007-07-30
申请人： Meikei Ieong , Min Yang
发明人： Meikei Ieong , Min Yang
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207 , Y10S438/973
摘要： The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.
摘要翻译：本发明提供了一种集成半导体器件的方法，使得在混合基板的特定晶体取向上形成不同类型的器件，其增强了每种器件的性能。具体地，本发明提供了一种集成半导体器件的方法，使得pFET位于（110）晶面上，而nFET位于平面混合衬底的（100）晶面上。本发明的方法还通过埋层绝缘体和反掺杂层的组合来改进制造SOI类器件的性能。本发明还涉及利用本发明的方法形成的半导体结构。

74. 发明授权

US07413941B2 Method of fabricating sectional field effect devices 有权
标题翻译：制造截面场效应装置的方法
公开(公告)号：US07413941B2
公开(公告)日：2008-08-19
申请号：US11433806
申请日：2006-05-13
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

75. 发明申请

US20080171423A1 LOW-COST STRAINED SOI SUBSTRATE FOR HIGH-PERFORMANCE CMOS TECHNOLOGY 有权
标题翻译：用于高性能CMOS技术的低成本应变SOI衬底
公开(公告)号：US20080171423A1
公开(公告)日：2008-07-17
申请号：US11622543
申请日：2007-01-12
申请人： Meikei Ieong , Douglas C. La Tulipe , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
发明人： Meikei Ieong , Douglas C. La Tulipe , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
IPC分类号： H01L21/20
CPC分类号： H01L21/02658 , H01L21/02667 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.
摘要翻译：提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力电影。由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

76. 发明授权

US07348611B2 Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof 有权
标题翻译：旋转晶片上的应变互补金属氧化物半导体（CMOS）及其方法
公开(公告)号：US07348611B2
公开(公告)日：2008-03-25
申请号：US11112820
申请日：2005-04-22
申请人： Meikei Ieong , Qiqing C. Ouyang , Kern Rim
发明人： Meikei Ieong , Qiqing C. Ouyang , Kern Rim
IPC分类号： H01L29/73
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

77. 发明申请

US20080044966A1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN 有权
公开(公告)号：US20080044966A1
公开(公告)日：2008-02-21
申请号：US11924024
申请日：2007-10-25
申请人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

78. 发明申请

US20080042202A1 QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS 审中-公开
标题翻译： QUASI自对准源/漏极FinFET工艺
公开(公告)号：US20080042202A1
公开(公告)日：2008-02-21
申请号：US11874753
申请日：2007-10-18
申请人： Meikei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
发明人： Meikei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66818 , H01L29/785
摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.
摘要翻译：提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。本发明还涉及利用本发明的方法形成的所得半导体结构。

79. 发明申请

US20070287224A1 THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN 失效
标题翻译：三维集成电路和设计方法
公开(公告)号：US20070287224A1
公开(公告)日：2007-12-13
申请号：US11737598
申请日：2007-04-19
申请人： Syed Alam , Ibrahim Elfadel , Kathryn Guarini , Meikei Ieong , Prabhakar Kudva , David Kung , Mark Lavin , Arifur Rahman
发明人： Syed Alam , Ibrahim Elfadel , Kathryn Guarini , Meikei Ieong , Prabhakar Kudva , David Kung , Mark Lavin , Arifur Rahman
IPC分类号： H01L21/02
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/84 , H01L27/1203
摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
摘要翻译：三维（3D）集成电路（IC），3D IC芯片和制造3D IC芯片的方法。该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

80. 发明申请

US20070246753A1 Metal gated ultra short MOSFET devices 有权
标题翻译：金属门极超短MOSFET器件
公开(公告)号：US20070246753A1
公开(公告)日：2007-10-25
申请号：US11407473
申请日：2006-04-20
申请人： Jack Chu , Bruce Doris , Meikei Ieong , Jing Wang
发明人： Jack Chu , Bruce Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

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