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71. 发明授权

US06882231B2 Adjustable frequency oscillator with programmable calibrating circuit and related system and method 有权
标题翻译：具有可编程校准电路的可调频振荡器及相关系统及方法
公开(公告)号：US06882231B2
公开(公告)日：2005-04-19
申请号：US10406628
申请日：2003-04-02
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： H03K3/03 , H03L7/00 , H03B27/00
CPC分类号： H03K3/0315 , H03L7/00
摘要： An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.
摘要翻译：可变频振荡电路包括：奇数个反相器连接成一个环路; 多个电容元件，各自连接到各个逆变器的输出端子; 以及输出端子，其提供以振荡频率振荡的信号。振荡器电路还包括校准电路，用于校准可由反相器传送到各个电容元件的最大电流。

72. 发明申请

US20050068803A1 Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator 有权
公开(公告)号：US20050068803A1
公开(公告)日：2005-03-31
申请号：US10651019
申请日：2003-08-28
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C11/00 , G11C11/34 , G11C16/12
CPC分类号： G11C16/12
摘要： A method for controlling programming voltage levels of non-volatile memory cells comprises: providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage level; and providing a reference cell crossed by a cell current. Advantageously according to an embodiment of the invention the cell current is applied to the resistive divider to correlate the programming voltage level to the intrinsic features of the reference cell. A programming voltage regulator of non-volatile memory cells comprises at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with its output terminal, to a resistive divider, inserted in turn between a programming voltage reference and the second voltage reference and connected to at least an output terminal of the regulator, effective to supply the programming voltage to the non-volatile memory cells. Advantageously according to an embodiment of the invention, the output terminal of the input stage is connected to a first circuit node of the resistive divider in correspondence with an end of a resistive element comprised in the resistive divider and having a further end connected to the programming voltage reference. In such a way, a voltage value obtained by shunting the programming voltage reference is applied at the first circuit node. The voltage regulator according to embodiments of the invention can be used in two-level contexts and in multilevel contexts, even for parallel programming of several multilevel memory cells.

73. 发明授权

US06683808B2 String programmable nonvolatile memory with NOR architecture 有权
标题翻译：具有NOR架构的字符串可编程非易失性存储器
公开(公告)号：US06683808B2
公开(公告)日：2004-01-27
申请号：US10179553
申请日：2002-06-24
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C8/10
摘要： A nonvolatile memory having a NOR architecture has a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines; and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.
摘要翻译：具有NOR结构的非易失性存储器具有存储器阵列，其包括以NOR形状排列成行和列的多个存储单元，布置在同一列上的存储单元连接到多个位线之一; 和列解码器。列解码器包括多个选择级，每个选择级连接到相应的位线并且接收第一位线寻址信号。选择级包括由第一位线寻址信号控制的字编程选择器，并将编程电压提供给每个选择级的仅一位位线。每个选择级还包括由第二位线寻址信号控制的串编程选择电路，从而同时将编程电压提供给每个选择级的多个位线。

74. 发明授权

US06570216B1 EEPROM having a peripheral integrated transistor with thick oxide 有权
标题翻译： EEPROM具有具有厚氧化物的外围集成晶体管
公开(公告)号：US06570216B1
公开(公告)日：2003-05-27
申请号：US09675753
申请日：2000-09-29
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： H01L29792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (21) having an active area (7) in regions peripheral to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5), the polysilicon (5) from the active area (7) of the thick-oxide transistor (21), so that the gate oxide of the transistor (21) results from the superposition of the first (4) and second (9) dielectric layers.
摘要翻译：一种用于制造集成电路的工艺提供了形成具有双重多晶硅层级的浮栅非易失性存储单元矩阵，其中两个多晶硅层由栅极介电层（4）和多晶硅间介电层（9）隔离），并且用于在基体周边的区域中同时形成具有有源区（7）的一种类型的厚氧化物晶体管（21）。本发明的方法提供了在从厚氧化物晶体管（21）的有源区域（7）定义第一级多晶硅（5），多晶硅（5）的步骤期间去除栅极氧化物晶体管（21）由第一（4）和第二（9）电介质层的叠加产生。

75. 发明授权

US06301157B1 Method and circuit for testing memory cells in a multilevel memory device 失效
标题翻译：用于测试多电平存储器件中的存储单元的方法和电路
公开(公告)号：US06301157B1
公开(公告)日：2001-10-09
申请号：US09415024
申请日：1999-10-07
申请人： Marco Riva , Paolo Rolandi , Massimo Montanaro
发明人： Marco Riva , Paolo Rolandi , Massimo Montanaro
IPC分类号： G11C1606
CPC分类号： G11C29/50 , G06F2201/81 , G11C11/56 , G11C11/5642 , G11C2029/5006 , G11C2211/5634
摘要： A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells. The method includes reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.
摘要翻译：一种用于在具有多个存储器单元的多电平存储器件中测试存储器单元，特别是处理存储器单元的方法。该方法包括读取构成存储器件的各个存储器单元，并且每次将这些存储器单元中的每一个与至少一个参考存储器单元进行比较，以便确定存储器单元的阈值是否低于至少一个参考存储器单元; 确定其阈值高于所述至少一个参考小区的阈值的存储器单元的数量; 所述至少一个参考存储器单元被选择为具有逐渐更高的阈值; 当阈值高于给定参考阈值的存储单元的数量被发现足够低于设置在存储器件中的冗余存储单元的数量时，假定给定参考阈值为存储器件的较低参考阈值，则确定存储单元阈值的统计分布。

76. 发明授权

US06198660B1 Synchronous multilevel non-volatile memory and related reading method 有权
标题翻译：同步多级非易失性存储器及相关读取方式
公开(公告)号：US06198660B1
公开(公告)日：2001-03-06
申请号：US09572127
申请日：2000-05-17
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C1604
CPC分类号： G11C7/1072 , G11C5/025 , G11C8/00 , G11C11/56 , G11C11/5621 , G11C11/5642 , G11C16/08
摘要： The memory and method for reading include a synchronous multilevel non-volatile memory with cell addresses which define a pair of memory cells on different planes of the multilevel memory and plane addresses which define the plane on which the memory cell defined by a memory cell address is to be read. The memory and method include switching the plane address at a preset time interval after the switching of a memory address and at the highest possible switching frequency, and reading the content of a memory location, from the memory, which corresponds to the memory address on planes alternatively indicated by the switching of the plane address.
摘要翻译：用于读取的存储器和方法包括具有单元地址的同步多电平非易失性存储器，其定义多层存储器的不同平面上的一对存储器单元和限定由存储器单元地址定义的存储器单元的平面的平面地址要读存储器和方法包括在切换存储器地址并且以最高可能的切换频率之后以预设的时间间隔切换平面地址，并且从存储器读取对应于平面上的存储器地址的存储器位置的内容或者通过切换飞机地址来指示。

77. 发明授权

US6156610A Process for manufacturing an EEPROM having a peripheral transistor with thick oxide 失效
标题翻译：用于制造具有厚氧化物的外围晶体管的EEPROM的工艺
公开(公告)号：US6156610A
公开(公告)日：2000-12-05
申请号：US840327
申请日：1997-04-28
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/8238 , H01L21/336 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (21) having an active area (7) in regions peripheral to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5), the polysilicon (5) from the active area (7) of the thick-oxide transistor (21), so that the gate oxide of the transistor (21) results from the superposition of the first (4) and second (9) dielectric layers.
摘要翻译：一种用于制造集成电路的工艺提供了形成具有双重多晶硅层级的浮栅非易失性存储单元矩阵，其中两个多晶硅层由栅极介电层（4）和多晶硅间介电层（9）隔离），并且用于在基体周边的区域中同时形成具有有源区（7）的一种类型的厚氧化物晶体管（21）。本发明的方法提供了在从厚氧化物晶体管（21）的有源区域（7）定义第一级多晶硅（5），多晶硅（5）的步骤期间去除栅极氧化物晶体管（21）由第一（4）和第二（9）电介质层的叠加产生。

78. 发明授权

US6115801A Device and method for increasing the internal address of a memory device using multifunctional terminals 失效
标题翻译：使用多功能终端增加存储设备的内部地址的设备和方法
公开(公告)号：US6115801A
公开(公告)日：2000-09-05
申请号：US49858
申请日：1998-03-27
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C5/06 , G06F12/00
CPC分类号： G11C5/066
摘要： A semiconductor integrated, storage circuit device having at least a first enable terminal for enabling the device, and a first number of address terminals for inputting an external address formed of a corresponding first number of bits. The device comprises a plurality of data storage elements which are addressable by an internal address formed of a second number of bits larger than said first number, and further comprises address storage elements which are coupleable with their inputs to the first enable terminal for storing additional address bits. Thus, the internal address is comprised of the external address and the additional address bits.
摘要翻译：一种半导体集成存储电路装置，具有至少一个用于启用该装置的第一使能端子以及用于输入由相应的第一位数形成的外部地址的第一数量的地址端子。所述设备包括多个数据存储元件，所述多个数据存储元件可由通过大于所述第一数量的第二数量位形成的内部地址寻址，并且还包括可与其输入耦合到所述第一使能端的地址存储元件，用于存储附加地址位。因此，内部地址由外部地址和附加地址位构成。

79. 发明授权

US6016271A Method and circuit for generating a gate voltage in non-volatile memory devices 有权
标题翻译：用于在非易失性存储器件中产生栅极电压的方法和电路
公开(公告)号：US6016271A
公开(公告)日：2000-01-18
申请号：US141250
申请日：1998-08-27
申请人： Paolo Rolandi , Roberto Gastaldi , Cristiano Calligaro
发明人： Paolo Rolandi , Roberto Gastaldi , Cristiano Calligaro
IPC分类号： G11C11/56 , G11C16/08 , G11C16/30 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/08 , G11C16/30 , G11C2211/5634 , G11C29/00 , G11C8/14
摘要： A circuit generates a regulated voltage, in particular for gate terminals of non-volatile memory cells of the floating gate type. The circuit includes a generator circuit adapted to generate an unregulated voltage on its output. A comparator circuit is coupled to the output of the generator circuit including a reference element including a non-volatile memory cell of the floating gate type and adapted to output an error signal tied to the difference between the unregulated voltage and the threshold voltage of the cell. A regulator circuit is coupled to the output of the comparator circuit and is operative to regulate the unregulated voltage based on the value of the error signal. The regulated voltage is made programmable and tied to the parameters of the memory cell.
摘要翻译：电路产生调节电压，特别是对浮栅型非易失性存储单元的栅极端子。电路包括适于在其输出上产生未调节电压的发生器电路。比较器电路耦合到发生器电路的输出端，该输出包括一个参考元件，该参考元件包括一个浮动型的非易失性存储单元，并且适于输出一个与非稳态电压和该单元的阈值电压之间的差值相关的误差信号。调节器电路耦合到比较器电路的输出，并且可操作以基于误差信号的值来调节未调节的电压。调节电压是可编程的，并且与存储器单元的参数相关联。

80. 发明授权

US5883837A Reading circuit for semiconductor memory cells 失效
公开(公告)号：US5883837A
公开(公告)日：1999-03-16
申请号：US940115
申请日：1997-09-29
申请人： Cristiano Calligaro , Paolo Rolandi , Roberto Gastaldi , Guido Torelli
发明人： Cristiano Calligaro , Paolo Rolandi , Roberto Gastaldi , Guido Torelli
IPC分类号： G11C11/413 , G11C7/06 , G11C11/56 , G11C16/06 , G11C16/04
CPC分类号： G11C7/062 , G11C11/5621 , G11C11/5642 , G11C7/065 , G11C7/06
摘要： A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

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