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71. 发明申请

US20110103135A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20110103135A1
公开(公告)日：2011-05-05
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

72. 发明申请

US20110066878A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110066878A1
公开(公告)日：2011-03-17
申请号：US12884965
申请日：2010-09-17
申请人： Koji Hosono , Yuri Terada , Takahiko Sasaki
发明人： Koji Hosono , Yuri Terada , Takahiko Sasaki
IPC分类号： G06F11/16 , G11C11/21
CPC分类号： G11C7/1015
摘要： A semiconductor storage device includes a memory cell array including memory cells arranged at respective intersections between first wirings and second wirings. Each of the memory cells includes a rectifier element and a variable resistance element connected in series. A control circuit is configured to apply a first voltage to a selected first wiring and a second voltage lower than the first voltage to a selected second wiring so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring.The control circuit performs a concurrent read operation to perform a read operation from plural memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently. It is possible to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.
摘要翻译：半导体存储装置包括存储单元阵列，该存储单元阵列包括布置在第一布线和第二布线之间的相应交点处的存储单元。每个存储单元包括串联连接的整流元件和可变电阻元件。控制电路被配置为将第一电压施加到所选择的第一布线和低于第一电压的第二电压到所选择的第二布线，使得某一电位差被施加到位于所选择的第一布线之间的交叉点处的选定存储单元接线和选定的第二个接线。控制电路通过同时向多个第一布线施加第一电压来执行同时读取操作，以同时从多个存储单元执行读取操作。可以在同时读取操作中同时切换要应用第一电压的第一布线的数量。

73. 发明授权

US07835182B2 Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices 有权
标题翻译：非易失性半导体存储器件以及在非易失性半导体存储器件中写入数据的方法
公开(公告)号：US07835182B2
公开(公告)日：2010-11-16
申请号：US12493744
申请日：2009-06-29
申请人： Koji Hosono
发明人： Koji Hosono
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other. In this mode, a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched, at least in two stages, between a lower voltage V1 than a write non-selection voltage Vm applied to other non-selected memory cells in the NAND cell unit and a higher voltage V2 than the lower voltage (V1
摘要翻译：器件具有数据写入模式以升高包含非写入选择存储单元的第一升压沟道区和位于更接近第一选择栅晶体管的非选择存储单元，以及包含未选择存储器的第二升压沟道区位于比选择的存储单元更靠近第二选择栅极晶体管的单元，彼此电分离。在该模式中，施加到第二选择栅极晶体管旁边的未选择的存储单元的写入非选择电压至少两级在施加于其它的写入非选择电压Vm的较低电压V1之间切换 NAND单元单元中的未选择的存储单元和比低电压（V1

74. 发明申请

US20100214850A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING DATA THEREIN 有权
标题翻译：半导体存储器件及其数据擦除方法
公开(公告)号：US20100214850A1
公开(公告)日：2010-08-26
申请号：US12773280
申请日：2010-05-04
申请人： Koji Hosono
发明人： Koji Hosono
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3404 , G11C16/344
摘要： A semiconductor memory device includes a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line and a source line, respectively. The semiconductor memory device also includes dummy cells inserted in the NAND cell unit adjacent to the first and second selection transistors, respectively. The dummy cells in the NAND cell unit are erased simultaneously with the memory cells under a weaker erase potential condition than that for the memory cells and set in a higher threshold distribution than an erased state of the memory cells.
摘要翻译：半导体存储器件包括NAND单元单元的存储单元阵列。 NAND单元单元包括串联连接的多个电可擦除可编程非易失性存储单元，以及分别将存储单元的两端连接到位线和源极线的第一和第二选择晶体管。半导体存储器件还包括分别插入与NAND单元单元相邻的第一和第二选择晶体管的虚拟单元。与存储单元相比，NAND单元单元中的虚设单元与存储单元同时擦除，而且存储单元的擦除电位低于存储单元，并且设置在比存储单元的擦除状态更高的阈值分布。

75. 发明授权

US07678510B2 Mask for exposure and method of manufacturing the same 有权
标题翻译：曝光掩模及其制造方法
公开(公告)号：US07678510B2
公开(公告)日：2010-03-16
申请号：US11017196
申请日：2004-12-21
申请人： Naoyuki Ishiwata , Koji Hosono
发明人： Naoyuki Ishiwata , Koji Hosono
IPC分类号： G03F1/00
CPC分类号： G03F1/44 , G03F1/30 , G03F1/80
摘要： There is provided a method of manufacturing a mask for exposure, which is capable of measuring the phase difference between a shifter portion and a non-shifter portion with good accuracy.A mask for exposure having: two first light-shielding device patterns, which are formed on a quartz substrate (transparent substrate) in a device region at a first gap and extend over a first concave portion; a second device light-shielding pattern at a second gap from the first device light-shielding pattern; two first light-shielding monitor patterns, which are formed on the quartz substrate in a monitor region at a third gap wider than the first gap and extend over a second concave portion; and second light-shielding monitor pattern, which has a fourth gap wider than the second gap from the first light-shielding monitor pattern, in which the size of the first light-shielding monitor pattern is equal to or less than the size of the first light-shielding device pattern.
摘要翻译：提供一种制造用于曝光的掩模的方法，其能够以高精度测量移位部分和非移动部分之间的相位差。一种用于曝光的掩模，具有：在第一间隙的器件区域中在石英衬底（透明衬底）上形成并在第一凹部上延伸的两个第一光屏蔽器件图案; 在与第一器件遮光图案的第二间隙处的第二器件遮光图案; 两个第一光屏蔽监视器图案，其形成在监视器区域中的石英衬底上，第三间隙比第一间隙宽，并延伸到第二凹部; 以及第二遮光监视器图案，其具有比第一遮光监视器图案的第二间隙宽的第四间隙，其中第一遮光监视器图案的尺寸等于或小于第一遮光监视器图案的尺寸遮光装置图案。

76. 发明授权

US07609558B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07609558B2
公开(公告)日：2009-10-27
申请号：US11530347
申请日：2006-09-08
申请人： Koji Hosono
发明人： Koji Hosono
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5642
摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page.
摘要翻译：非易失性半导体存储器件包括具有串联连接的多个多电平存储单元的存储单元阵列。多个多级存储器单元形成多个阈值分布，每个阈值分布对应于较低位的状态和高位的状态，其中低位和高位分别构成下部页面和上部页面。较低位的状态将阈值分布分为两组，高位的状态进一步将两组中的每一组进行二分。当对上部页面的存储单元进行编程时，当对下部页面的存储单元进行编程时，较高电位被施加到与所选字线相邻的未选择字线，而不是应用于未选择的字线。

77. 发明申请

US20090244978A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090244978A1
公开(公告)日：2009-10-01
申请号：US12408260
申请日：2009-03-20
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

78. 发明授权

US07561468B2 Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices 有权
标题翻译：非易失性半导体存储器件以及在非易失性半导体存储器件中写入数据的方法
公开(公告)号：US07561468B2
公开(公告)日：2009-07-14
申请号：US11857091
申请日：2007-09-18
申请人： Koji Hosono
发明人： Koji Hosono
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/3427
摘要： The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other. In this mode, a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched, at least in two stages, between a lower voltage V1 than a write non-selection voltage Vm applied to other non-selected memory cells in the NAND cell unit and a higher voltage V2 than the lower voltage (V1
摘要翻译：器件具有数据写入模式以升高包含非写入选择存储单元的第一升压沟道区和位于更接近第一选择栅晶体管的非选择存储单元，以及包含未选择存储器的第二升压沟道区位于比选择的存储单元更靠近第二选择栅极晶体管的单元，彼此电分离。在该模式中，施加到第二选择栅极晶体管旁边的未选择的存储单元的写入非选择电压至少两级在施加于其它的写入非选择电压Vm的较低电压V1之间切换 NAND单元单元中的未选择存储单元和比低电压（V1

79. 发明授权

US07524591B2 Photomask and manufacturing method thereof, fabrication process of an electron device 失效
标题翻译：光掩模及其制造方法，电子器件的制造工艺
公开(公告)号：US07524591B2
公开(公告)日：2009-04-28
申请号：US11126295
申请日：2005-05-11
申请人： Koji Hosono
发明人： Koji Hosono
IPC分类号： G03F1/00 , G03C5/00
CPC分类号： G03F1/50
摘要： A photomask made by using a negative photoresist includes a transparent substrate defined with a device chip area, an opaque device pattern formed on the transparent substrate in the device chip area, and a dummy opaque pattern provided on the transparent substrate outside of the device chip area.
摘要翻译：通过使用负性光致抗蚀剂制成的光掩模包括由器件芯片区域限定的透明衬底，在器件芯片区域中形成在透明衬底上的不透明器件图案，以及设置在器件芯片区域外部的透明衬底上的虚设不透明图案。

80. 发明申请

US20090010039A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090010039A1
公开(公告)日：2009-01-08
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

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