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    • 73. 发明申请
    • STORAGE SYSTEM
    • 存储系统
    • US20110296104A1
    • 2011-12-01
    • US13147672
    • 2009-08-20
    • Kenji NodaHiroyuki Tokutake
    • Kenji NodaHiroyuki Tokutake
    • G06F12/16
    • G06F11/1084G06F11/1088G06F2211/1028
    • A storage system includes: a distribution storage processing means configured to distribute and store a plurality of fragment data into a plurality of storing means; a data location monitoring means configured to monitor a data location status of the fragment data and store data location information representing the data location status; and a data restoring means configured to, when the storing means is down, regenerate the fragment data having been stored in the down storing means based on the fragment data stored in the other storing means. The storage system also includes: a data location returning means configured to, when the down storing means recovers, return a data location of the fragment data by using the fragment data stored in the storing means having recovered so that the data location status becomes as represented by the data location information stored by the data location monitoring means.
    • 存储系统包括:分发存储处理装置,被配置为将多个片段数据分发并存储到多个存储装置中; 数据位置监视装置,被配置为监视分段数据的数据位置状态并存储表示数据位置状态的数据位置信息; 以及数据恢复装置,被配置为当存储装置关闭时,基于存储在另一个存储装置中的片段数据,再现已经存储在下载存储装置中的片段数据。 存储系统还包括:数据位置返回装置,被配置为当下行存储装置恢复时,通过使用存储在已恢复的存储装置中的分段数据来返回分段数据的数据位置,使得数据位置状态变为表示 通过由数据位置监视装置存储的数据位置信息。
    • 74. 发明授权
    • Nonvolatile memory device storing data based on change in transistor characteristics
    • 基于晶体管特性变化存储数据的非易失性存储器件
    • US07835196B2
    • 2010-11-16
    • US12088971
    • 2005-10-03
    • Kenji Noda
    • Kenji Noda
    • G11C7/10
    • G11C16/0466G11C11/412G11C14/00G11C17/08
    • A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of the first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors.
    • 非易失性存储器件包括一对PMOS晶体管,以及控制电路,其被配置为以存储模式工作,以应用于导致NBTI劣化的第一个PMOS晶体管的电位,并且施加到第二个PMOS晶体管 不导致NBTI劣化的电位,同时在PMOS晶体管的第一个源极节点和漏极节点之间没有电流流动,并且以调用模式操作以将PMOS晶体管的栅极节点设置为共同的电位来检测 所述PMOS晶体管之间的NBTI劣化的差异。
    • 75. 发明申请
    • ENDOSCOPE APPARATUS
    • 内窥镜装置
    • US20100022834A1
    • 2010-01-28
    • US12180655
    • 2008-07-28
    • Kenji NodaMasatsugu Oyama
    • Kenji NodaMasatsugu Oyama
    • A61B1/015A61B1/12
    • A61B1/015
    • A gas supply source for supplying gas and a channel along which the gas is supplied can be easily switched by providing an instrument channel for passing an endoscope treating tool, a gas and water supply channel for supplying carbon dioxide etc. to the inside of a body, a gas supply source for a visceral cavity capable of supplying gas at a predetermined pressure, a gas supply source for a lumen capable of supplying gas at an optional pressure, and a switch device for switching from any of and an instrument channel and a gas and water supply channel to any of the gas supply source for a visceral cavity and the gas supply source for a lumen.
    • 用于供应气体的气体供应源和供应气体的通道可以通过提供用于将内窥镜处理工具,用于将二氧化碳等供应的气体和水供应通道提供给身体内部的仪器通道来容易地切换 用于能够以预定压力供应气体的内脏气体供应源,用于能够以任选压力供应气体的内腔的气体供应源,以及用于从仪器通道和气体中的任何一个切换的开关装置 以及用于内脏的任何气体供应源和用于管腔的气体供应源的供水通道。
    • 76. 发明授权
    • Nonvolatile memory utilizing MIS memory transistors with function to correct data reversal
    • 使用MIS存储晶体管的非易失性存储器具有校正数据反转的功能
    • US07639546B2
    • 2009-12-29
    • US12037414
    • 2008-02-26
    • Takashi KikuchiKenji Noda
    • Takashi KikuchiKenji Noda
    • G11C7/00
    • G11C7/1045G11C7/1006G11C7/12G11C14/00G11C14/0063
    • A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.
    • 非易失性半导体存储器件包括具有两个节点的锁存电路,包括两个MIS晶体管的非易失性存储器单元,配置成在第一操作模式期间在两个节点和两个MIS晶体管之间提供直连接并提供交叉连接 在第二操作模式期间在两个节点和两个MIS晶体管之间,以及控制电路,被配置为在第一和第二操作模式之一中使得非易失性存储单元将锁存在锁存电路中的数据存储为不可逆变化 的晶体管特性出现在所述两个MIS晶体管中的所选择的一个中,并且还被配置为在所述第一和第二操作模式中的另一个中引起所述锁存电路来检测存储在所述非易失性存储单元中的数据。
    • 77. 发明申请
    • Polybutylene terephthalate
    • 聚对苯二甲酸丁二醇酯
    • US20090264611A1
    • 2009-10-22
    • US10594668
    • 2005-03-29
    • Toshiyuki HamanoMasanori YamamotoShinichiro MatsuzonoKenji Noda
    • Toshiyuki HamanoMasanori YamamotoShinichiro MatsuzonoKenji Noda
    • C08G63/183C08G79/00
    • C08G63/85C08G63/183
    • Polybutylene terephthalate has an intrinsic viscosity of 0.7 to 1.0 dL/g and an end carboxyl group concentration of 0.1 to 18 μeq/g, which is produced in a presence of a catalyst comprising a titanium compound and a metal compound containing a metal of Group 2A of the Periodic Table. In the preferable embodiment of the present invention, the polybutylene terephthalate has a crystallization temperature of 170 to 195° C. as measured at a temperature drop rate of 20° C./min using a differential scanning calorimeter, an end vinyl group concentration of not more than 10 μeq/g, and not more than 10% of a solution haze of a solution prepared by dissolving 2.7 g of said polybutylene terephthalate in 20 mL of a mixed solvent containing phenol and tetrachloroethane at a weight ratio of 3:2.The polybutylene terephthalate of the present invention exhibits excellent color tone, hydrolysis resistance, heat stability, transparency and moldability as well as a less content of impurities, which is suitably applicable to films, monofilaments, fibers, electric and electronic parts, automobile parts, etc.
    • 聚对苯二甲酸丁二醇酯的特性粘度为0.7〜1.0dL / g,末端羧基浓度为0.1〜18mueq / g,其是在含有钛化合物和含有2A族金属的金属化合物的催化剂存在下制备的 的周期表。 在本发明的优选实施方案中,聚对苯二甲酸丁二醇酯的结晶温度为170〜195℃,使用差示扫描量热计,以20℃/分钟的降温速度测定,末端乙烯基浓度不为 通过将2.7g所述聚对苯二甲酸丁二醇酯溶解在20mL含有苯酚和四氯乙烷的混合溶剂中,以3:2的重量比制备的溶液的溶液雾度大于10emueq / g,不超过10%。 本发明的聚对苯二甲酸丁二醇酯显示出优异的色调,耐水解性,热稳定性,透明性和成型性以及较少的杂质含量,其适用于膜,单丝,纤维,电气和电子部件,汽车部件等 。
    • 78. 发明授权
    • Photomask and method for forming pattern
    • 光掩模和形成图案的方法
    • US07582394B2
    • 2009-09-01
    • US10957599
    • 2004-10-05
    • Kenji NodaShin Hashimoto
    • Kenji NodaShin Hashimoto
    • G03F1/00H01L21/00
    • G03F1/36
    • A photomask includes, on a translucent substrate, three or more first light-shielding portions each in insular shape having a property of shielding exposure light and spaced equidistantly, a second light-shielding portion having a property of shielding the exposure light and formed to connect the adjacent first light-shielding portions, and first light-transmitting portions each in slit shape having a property of transmitting the exposure light and formed to be surrounded with the first and second light-shielding portions. The second light-shielding portion is formed to contain a point located equidistantly from the three or more first light-shielding portions.
    • 一种光掩模在透光性基板上具有三个以上的具有隔离曝光光等间隔的特性的具有岛状的三个以上的第一遮光部,具有屏蔽曝光光的特性的第二遮光部,形成为连接 相邻的第一遮光部和具有透射曝光光的特性的狭缝状的第一透光部,形成为被第一和第二遮光部包围。 第二遮光部形成为包含与三个以上的第一遮光部等距离地设置的点。
    • 79. 发明授权
    • Nonvolatile memory utilizing MIS memory transistors capable of multiple store operations
    • 使用能够进行多个存储操作的MIS存储器晶体管的非易失性存储器
    • US07518917B2
    • 2009-04-14
    • US11775951
    • 2007-07-11
    • Kenji NodaTakashi Kikuchi
    • Kenji NodaTakashi Kikuchi
    • G11C11/34
    • G11C14/00G11C11/412
    • A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.
    • 非易失性半导体存储器件包括:锁存器,被配置为存储数据,多个字线,被配置为激活多个字线中的一个字线的驱动器;以及耦合到各个字线的多个非易失性存储器单元,每个非易失性存储器件 存储器单元耦合到所述锁存器,以便在激活相应的一条字线时与所述锁存器交换存储的数据,所述非易失性存储器单元中的每一个包括两个MIS晶体管,并且被配置为将数据存储为晶体管特性的不可逆变化, 两个MIS晶体管中的一个,其中驱动器包括至少一个非易失性存储单元,其存储响应于多次数据存储的数量的计数数据,并且被配置为激活多个非易失性存储单元中的一个, 字数由计数数据表示。