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71. 发明授权

US5340768A Method of fabricating self-aligned field-plate isolation between control electrodes 失效
标题翻译：在控制电极之间制造自对准场板隔离的方法
公开(公告)号：US5340768A
公开(公告)日：1994-08-23
申请号：US68047
申请日：1993-05-28
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L27/115 , H01L29/06 , H01L29/40 , H01L21/76
CPC分类号： H01L29/402 , H01L27/115
摘要： The structure and method of this invention provide, for example, electrical isolation between active elements in adjacent rows and/or columns of an integrated circuit by use of a self-aligned field-plate conductor formed over and insulated from the substrate regions that are bounded by the channel regions of field-effect transistors in adjacent rows and that are bounded by the bitlines forming those transistors in a column. The field-plate conductor is formed, for example, in a strip that extends over the isolation areas and thermal insulator regions between row lines of the memory cell array. The field-plate conductor strip is connected to a voltage supply that has a potential with respect to the potential of the semiconductor substrate which causes the isolation areas to be nonconductive. Component density may be increased over that of prior-art structures and methods.
摘要翻译：本发明的结构和方法提供了例如通过使用形成在被限定的衬底区域上并与之绝缘的自对准场致发射板导体的集成电路的相邻行和/或列中的有源元件之间的电隔离通过相邻行中的场效应晶体管的沟道区域并且由在列中形成那些晶体管的位线限定。场板导体例如形成在隔离区域上延伸的条带和存储单元阵列的行线之间的绝热体区域。场板导体条连接到电压源，该电压源相对于半导体衬底的电位具有电位，这导致隔离区域不导电。组分密度可以比现有技术的结构和方法增加。

72. 发明授权

US5150179A Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and method for making and using the same 失效
标题翻译：无扩散源/漏导体电可擦除，电可编程只读存储器及其制造和使用方法
公开(公告)号：US5150179A
公开(公告)日：1992-09-22
申请号：US548045
申请日：1990-07-05
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L29/66825 , G11C16/0491 , H01L27/115 , H01L27/11517 , H01L29/7883
摘要： A diffusionless source/drain conductor, electrically-erasable, electrically-programmable read-only memory cell is formed at a face of a semiconductor layer (38) of a first conductivity type and includes a source conductor (10), a drain conductor (12), a channel region (18), and a tunnel region (22). Source conductor (10) and drain conductor (12) are disposed to create inversion regions, of a second conductivity type, opposite said first conductivity type, in the source inversion region (14) and drain inversion region (16) of semiconductor layer (38) of the layer semiconductor, upon application of voltage. Thin oxide tunneling window (22) is disposed adjacent source conductor (10). A floating gate (24) disposed adjacent tunneling window can be charged or discharged by Fowler-Nordheim tunneling when a voltage is applied between the inversion created in source inversion region (14) and a control gate (26) insulatively adjacent floating gate (24).
摘要翻译：在第一导电类型的半导体层（38）的表面上形成无电解源/漏导体，电可擦除的电可编程只读存储单元，并且包括源极导体（10），漏极导体（12）），通道区域（18）和隧道区域（22）。源极导体（10）和漏极导体（12）设置成在半导体层（38）的源极反向区域（14）和漏极反转区域（16）中产生与第一导电类型相反的第二导电类型的反转区域）施加电压。薄氧化物隧道窗（22）邻近源极导体（10）设置。当在源反转区域（14）产生的反相与绝对相邻的浮动栅极（24）之间的控制栅极（26）之间施加电压时，可以通过Fowler-Nordheim隧道对位于隧道窗附近的浮动栅极（24）进行充电或放电，。

73. 发明授权

US5147816A Method of making nonvolatile memory array having cells with two tunelling windows 失效
标题翻译：制造具有两个延伸窗口的单元的非易失性存储器阵列的方法
公开(公告)号：US5147816A
公开(公告)日：1992-09-15
申请号：US736338
申请日：1991-07-26
申请人： Manzur Gill , Theodore D. Lindgren
发明人： Manzur Gill , Theodore D. Lindgren
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , Y10S438/981
摘要： A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first, second and third sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned over and insulated from the floating gates of the cells for reading, programming and erasing the cells. The row lines, including control gates, are also positioned over and insulated from the third sub-channels. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
摘要翻译：具有用于编程和擦除的分离区域的非易失性存储单元。电池在半导体本体的表面上以阵列形成，每个电池包括作为源 - 列线的一部分的源，并且包括作为漏 - 列线的一部分的漏极。每个单元在源极和漏极之间具有第一，第二和第三子通道。每个电池单元的第一子通道的电导率由场板控制，该场板是位于第一子通道上并与第一子通道绝缘的场板 - 列 - 列线的一部分。每个第二子通道的电导率由形成在第二子通道上并与第二子通道绝缘的浮动栅极控制。每个浮动栅极具有位于相邻源极列线上方的第一隧道窗口，并且具有位于相邻排列 - 列线上方的第二隧道窗口。包括控制栅极的行线位于单元的浮动栅极上并与其隔离，用于读取，编程和擦除单元。包括控制栅极的行线也位于第三子通道上并与第三子通道绝缘。场板导体仅允许通过第一隧道窗口对单元进行编程，并且仅通过第二隧道窗口擦除单元，反之亦然。

74. 发明授权

US5134449A Nonvolatile memory cell with field-plate switch 失效
标题翻译：具有场板开关的非易失性存储单元
公开(公告)号：US5134449A
公开(公告)日：1992-07-28
申请号：US661590
申请日：1991-02-26
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provides isolation of the cells during programming.
摘要翻译：在半导体本体的表面上形成非易失性存储单元的阵列，该单元包括源极区，并且包括作为公共漏极列导体的一部分的漏极区。每个单元在源极和漏极之间具有第一和第二子沟道区。每个单元的第一子沟道区的导电性由形成在第一子沟道区上并与第一子沟道区绝缘的场板导体控制。每个第二子沟道区的导电性由形成在第二子沟道区上并与第二子沟道区绝缘的浮栅导体控制。包括控制栅极的行线位于单元的浮动栅极的上方并与之隔绝，用于读取，编程和擦除单元。场板导体开关在编程过程中提供了单元的隔离。

75. 发明授权

US5032533A Method of making a nonvolatile memory cell with field-plate switch 失效
标题翻译：制造具有场板开关的非易失性存储单元的方法
公开(公告)号：US5032533A
公开(公告)日：1991-07-16
申请号：US444585
申请日：1989-12-04
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , Y10S438/981
摘要： An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provided isolation of the cells during programming.
摘要翻译：在半导体本体的表面上形成非易失性存储单元的阵列，该单元包括源极区，并且包括作为公共漏极列导体的一部分的漏极区。每个单元在源极和漏极之间具有第一和第二子沟道区。每个单元的第一子沟道区的导电性由形成在第一子沟道区上并与第一子沟道区绝缘的场板导体控制。每个第二子沟道区的导电性由形成在第二子沟道区上并与第二子沟道区绝缘的浮栅导体控制。包括控制栅极的行线位于单元的浮动栅极的上方并与之隔绝，用于读取，编程和擦除单元。场板导体开关在编程期间提供了单元的隔离。

76. 发明授权

US5023680A Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates 失效
标题翻译：具有硅化掩埋位线和单步定义浮动栅极的浮栅存储器阵列
公开(公告)号：US5023680A
公开(公告)日：1991-06-11
申请号：US269836
申请日：1988-11-10
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L29/7886 , H01L27/115 , H01L29/7881 , H01L29/7883
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。字线之间和位线之间的隔离是厚场氧化物区域。一个厚场氧化物条将每个接地导线/位线对分开。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。浮动栅极的四个侧面被定义为单个图案化步骤。所得到的结构是可编程存储器单元的密集交叉点阵列。

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