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    • 76. 发明申请
    • Global synchronization method and system based on packet switching system
    • 基于分组交换系统的全局同步方法和系统
    • US20150010022A1
    • 2015-01-08
    • US14369332
    • 2011-12-27
    • Wei Huang
    • Wei Huang
    • H04L7/00
    • H04L7/0016H04J3/0658H04L49/40
    • A global synchronization method based on a packet switching system includes that: a reference chip is selected; and each chip calibrates its own timer by taking the reference chip as a reference, wherein each chip sends a zero-point pulse or zero-point pulse cell to each high-speed link (serdes) connected with the chip, and feeds back a calibration cell in response to a zero-point pulse or zero-point pulse cell received through each high-speed link. Accordingly, a global synchronization system based on a packet switching system is also disclosed. The disclosure reduces the packet loss rate and increases the accuracy of calibration.
    • 基于分组交换系统的全局同步方法包括:选择参考芯片; 并且每个芯片通过以参考芯片为参考来校准其自己的定时器,其中每个芯片向与芯片连接的每个高速链路(serdes)发送零点脉冲或零点脉冲单元,并且反馈校准 响应于通过每个高速链路接收的零点脉冲或零点脉冲单元。 因此,还公开了一种基于分组交换系统的全球同步系统。 该公开内容降低了丢包率并提高了校准的准确性。
    • 79. 发明授权
    • Quad-data rate controller and implementing method thereof
    • 四数据速率控制器及其实现方法
    • US08751853B2
    • 2014-06-10
    • US13496606
    • 2010-12-22
    • Jishan DingWei HuangWei LaiJianbing WangKedong YuZhiyong Liao
    • Jishan DingWei HuangWei LaiJianbing WangKedong YuZhiyong Liao
    • G06F1/12
    • G06F13/1689
    • A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module. The arbiter arbitrates commands and data according to the state of the control state machine; the read data sampling clock generating module generates read data sampling clocks with the same source and same frequency and different phases; the read data path calibrating module determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; the read data path module synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks. The present invention has a shorter delay and does not need any programmable delay element, and is easy to implement.
    • 在本发明中公开了四数据速率(QDR)控制器及其实现方法。 该控制器包括:仲裁器,控制状态机,读取数据采样时钟产生模块,读取数据路径模块和读取数据路径校准模块。 仲裁者根据控制状态机的状态对命令和数据进行仲裁; 读数据采样时钟产生模块产生具有相同源和相同频率和不同相位的读数据采样时钟; 读取数据路径校准模块在所生成的读取数据采样时钟中,确定读取数据路径模块的正边缘数据和下降沿数据的采样时钟,以便当控制状态机处于“读取数据路径 校正状态“ 读取数据路径模块根据确定的采样时钟将非系统时钟域中的正沿读取数据和下降沿数据同步到系统时钟域。 本发明具有更短的延迟并且不需要任何可编程延迟元件,并且易于实现。