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71. 发明申请

US20130075855A1 Manufacturing methods for accurately aligned and self-balanced superjunction devices 有权
标题翻译：精确对准和自平衡超级结装置的制造方法
公开(公告)号：US20130075855A1
公开(公告)日：2013-03-28
申请号：US13200683
申请日：2011-09-27
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06 , H01L21/22
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
摘要翻译：一种在半导体基板上制造半导体功率器件的方法，该半导体衬底通过生长第一外延层，然后在外延层的顶部上形成第一硬掩模层，从而支撑由外延层组成的漂移区; 施加第一注入掩模以打开多个植入窗口并且施加第二注入掩模以阻挡所述植入物窗口中的一些以在所述第一外延层中相互邻近地注入交替导电类型的多个掺杂区域; 通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤，以形成多个外延层，然后利用扩散处理在外延层的顶侧上进行器件制造工艺，以将掺杂区域交替导电类型作为外延层中的掺杂列。

72. 发明授权

US08390058B2 Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions 有权
标题翻译：用于制造具有沟槽氧化物 - 纳米管超结的器件的配置和方法
公开(公告)号：US08390058B2
公开(公告)日：2013-03-05
申请号：US12661004
申请日：2010-03-05
申请人： Hamza Yilmaz , Madhur Bobde , Yeeheng Lee , Lingpeng Guan , Xiaobin Wang , John Chen , Anup Bhalla
发明人： Hamza Yilmaz , Madhur Bobde , Yeeheng Lee , Lingpeng Guan , Xiaobin Wang , John Chen , Anup Bhalla
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7397 , H01L29/0661 , H01L29/66348
摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.
摘要翻译：本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。可以在第一外延层上生长第二外延层。每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

73. 发明申请

US20120329238A1 Method For Forming A Transient Voltage Suppressor Having Symmetrical Breakdown Voltages 有权
标题翻译：形成具有对称击穿电压的瞬态电压抑制器的方法
公开(公告)号：US20120329238A1
公开(公告)日：2012-12-27
申请号：US13604834
申请日：2012-09-06
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
IPC分类号： H01L21/302 , H01L21/265
CPC分类号： H01L29/861 , H01L27/0259 , H01L29/10 , H01L29/6609
摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.
摘要翻译：垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底是重掺杂的，第一导电类型的外延层形成在衬底上，其中外延层具有第一厚度;以及基极区形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。在一个实施例中，通过高能量注入形成基极区域。在另一个实施例中，基底区形成为掩埋层。选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。

74. 发明申请

US20120248566A1 Configuration and method to generate saddle junction electric field in edge termination 有权
标题翻译：在边缘终端中产生鞍形电场的配置和方法
公开(公告)号：US20120248566A1
公开(公告)日：2012-10-04
申请号：US13065824
申请日：2011-03-29
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.
摘要翻译：本发明公开了一种半导体功率器件，其设置在半导体衬底中，并具有有源电池区域和边缘终端区域的边缘终端区域，其中边缘终端区域包括具有交替导电类型的掺杂半导体柱的超结构结构，其中电荷不平衡掺杂的半导体柱在边缘终端中产生鞍形电场。

75. 发明申请

US20120193676A1 Diode structures with controlled injection efficiency for fast switching 有权
标题翻译：具有控制注入效率的二极管结构，实现快速切换
公开(公告)号：US20120193676A1
公开(公告)日：2012-08-02
申请号：US12931429
申请日：2011-01-31
申请人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
发明人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
IPC分类号： H01L29/72 , H01L21/331
CPC分类号： H01L29/7391
摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体器件。半导体器件包括在第一主表面上的第一导电类型的第一半导体层。半导体器件还包括在与第一主表面相对的第二主表面上的第二导电类型的第二半导体层。该半导体器件还包括设置在第二半导体层正下方的第一导电类型的注入效率控制缓冲层，以控制第二半导体层的注入效率。

76. 发明申请

US20110127606A1 Lateral super junction device with high substrate-drain breakdwon and built-in avalanche clamp diode 有权
标题翻译：具有高衬底漏极断路和内置雪崩钳位二极管的横向超接线装置
公开(公告)号：US20110127606A1
公开(公告)日：2011-06-02
申请号：US12592619
申请日：2009-11-30
申请人： Madhur Bobde , Anup Bhalla , Hamza Yilmaz , Wilson Ma , Lingpeng Guan , Yeeheng Lee , John Chen
发明人： Madhur Bobde , Anup Bhalla , Hamza Yilmaz , Wilson Ma , Lingpeng Guan , Yeeheng Lee , John Chen
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0705 , H01L29/0634 , H01L29/66901 , H01L29/808 , H01L2224/0603 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： This invention discloses configurations and methods to manufacture lateral power device including a super junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.
摘要翻译：本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极与栅极之间形成的具有雪崩钳位二极管的超结结构。横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。

77. 发明申请

US20110127586A1 Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode 有权
标题翻译：具有高基板栅极击穿和内置雪崩钳位二极管的横向超接点器件
公开(公告)号：US20110127586A1
公开(公告)日：2011-06-02
申请号：US12799810
申请日：2010-04-30
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L27/06 , H01L21/8232
CPC分类号： H01L29/808 , H01L29/0626 , H01L29/0634 , H01L29/0696 , H01L29/0843 , H01L29/0878 , H01L29/0882 , H01L29/1066 , H01L29/1095 , H01L29/4175 , H01L29/41766 , H01L29/4238 , H01L29/66696 , H01L29/66901 , H01L29/7817 , H01L29/7821
摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
摘要翻译：横向超结JFET由负载在N +衬底上的P表面层上的堆叠的交替P型和N型半导体层形成。 N +漏极柱向下延伸穿过超结结构和P-epi以连接到N +衬底以使器件成为底部漏极器件。 N +源极柱和P +栅极柱延伸穿过超级结，但在P-epi层处停止。栅极 - 漏极雪崩钳位二极管从P +栅极底部通过P-epi到N +漏极衬底形成。

78. 发明申请

US20110101446A1 STAGGERED COLUMN SUPERJUNCTION 有权
公开(公告)号：US20110101446A1
公开(公告)日：2011-05-05
申请号：US12610052
申请日：2009-10-30
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Hamza Yilmaz
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/7802 , H01L29/7811
摘要： A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.
摘要翻译：交错列超结半导体器件可以包括具有一个或多个器件单元的单元区域。单元区域中的一个或多个器件单元包括被配置为用作漏极的半导体衬底和形成在衬底上的半导体层。第一掺杂柱可以在半导体层中形成为第一深度，并且可以在半导体层中形成第二掺杂柱到第二深度。第一个深度大于第二个深度。第一和第二列掺杂有相同第二导电类型的掺杂剂并且沿着半导体层的厚度的一部分延伸并且由半导体层的一部分分离。

79. 发明申请

US20100244090A1 TVS with low capacitance & Forward voltage drop with depleted SCR as steering diode 有权
标题翻译：具有低电容和正向压降的TVS，具有作为转向二极管的耗尽的SCR
公开(公告)号：US20100244090A1
公开(公告)日：2010-09-30
申请号：US12384185
申请日：2009-03-31
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Limin Weng
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Limin Weng
IPC分类号： H01L29/866
CPC分类号： H01L29/866 , H01L27/0259 , H01L27/0814 , H01L27/0817 , H01L29/0657
摘要： A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.
摘要翻译：一种设置在第一导电类型的半导体衬底上的瞬态电压抑制（TVS）器件。 TVS包括第二导电类型的掩埋掺杂区域，其被布置和包围在第一导电类型的外延层中，其中掩埋掺杂剂区域横向延伸并且具有与外延层的下面部分接合的延伸的底部接合区域，从而构成用于TVS器件的齐纳二极管。 TVS器件还包括掩埋掺杂剂区域上方的区域，还包括第二导电类型的顶部掺杂剂层和第二导电类型的顶部接触区域，其与外延层和掩埋掺杂剂区域结合起来以形成多个连接构成SCR作为转向二极管的PN结与用于抑制瞬态电压的齐纳二极管起作用的PN结。

80. 发明申请

US20180138906A9 ROBUST SEMICONDUCTOR POWER DEVICES WITH DESIGN TO PROTECT TRANSISTOR CELLS WITH SLOWER SWITCHING SPEED 审中-公开
公开(公告)号：US20180138906A9
公开(公告)日：2018-05-17
申请号：US14585201
申请日：2014-12-30
申请人： Sik K. Lui , Anup Bhalla
发明人： Sik K. Lui , Anup Bhalla
IPC分类号： H03K17/687 , H01H49/00
CPC分类号： H01H49/00 , H01L29/0696 , H01L29/0856 , H01L29/086 , H01L29/7803 , H01L29/7813 , H01L2924/0002 , H03K17/04123 , H03K17/08122 , H03K17/122 , H03K17/164 , H03K17/687 , Y10T29/49105 , Y10T307/747 , Y10T307/76 , H01L2924/00
摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

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