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71. 发明授权

US06300658B1 Method for reduced gate aspect ration to improve gap-fill after spacer etch 有权
标题翻译：减少栅极比例的方法，以改善间隔蚀刻后的间隙填充
公开(公告)号：US06300658B1
公开(公告)日：2001-10-09
申请号：US09368073
申请日：1999-08-03
申请人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
发明人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76837 , H01L27/115
摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.
摘要翻译：本发明提供一种降低闪速存储器件的栅极纵横比的方法。该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。因此提高了装置的可靠性。

72. 发明授权

US06207552B1 Forming and filling a recess in interconnect for encapsulation to minimize electromigration 有权
标题翻译：在互连中形成和填充凹槽以进行封装以最小化电迁移
公开(公告)号：US06207552B1
公开(公告)日：2001-03-27
申请号：US09495843
申请日：2000-02-01
申请人： Pin-Chin C. Wang , Lu You
发明人： Pin-Chin C. Wang , Lu You
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/76801 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76877
摘要： A strong interface is fabricated by forming and filling a recess on top of an interconnect between the interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. A recess is formed within the top surface of the interconnect, and diffusion barrier material is deposited within the recess on the top surface of the interconnect. The diffusion barrier material may be epitaxially grown from the interconnect during the deposition of the diffusion barrier material within the recess to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer. The diffusion barrier material within the recess of the interconnect prevents lateral drift of material comprising the interconnect along the encapsulating layer. When the layer of encapsulating dielectric is comprised of silicon nitride, a nitrided surface may be formed on top of the diffusion barrier material by exposing the top of the diffusion barrier material to nitrogen plasma before depositing the encapsulating layer of silicon nitride on top of the diffusion barrier material. The present invention may be used to particular advantage when the interconnect is a copper interconnect and when the layer of encapsulating layer is comprised of silicon nitride.
摘要翻译：通过在互连和封装层之间的互连的顶部上形成并填充凹槽来制造强界面，以防止材料沿着封装层的底部从互连件侧向漂移。在互连的顶表面内形成一个凹槽，并且扩散阻挡材料沉积在互连顶表面上的凹槽内。扩散阻挡材料可以在凹陷内的扩散阻挡材料沉积期间从互连外延生长，以促进扩散阻挡材料与互连的粘合。封装层沉积在扩散阻挡材料的顶部上。扩散阻挡材料和封装层由类似的化学元素组成，以促进扩散阻挡材料与封装层的粘附。互连凹槽内的扩散阻挡材料防止沿着封装层的包括互连的材料的横向漂移。当封装电介质层由氮化硅组成时，可以在扩散阻挡材料的顶部上形成氮化表面，该方法是在将扩散阻挡材料的顶部暴露于氮等离子体之前，将氮化硅封装层沉积在扩散层顶部阻隔材料。当互连是铜互连并且当封装层由氮化硅构成时，本发明可以被用于特别的优点。

73. 发明申请

US20120007221A1 MASK FOR FORMING INTEGRATED CIRCUIT 有权
标题翻译：形成集成电路的掩模
公开(公告)号：US20120007221A1
公开(公告)日：2012-01-12
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L29/66 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

74. 发明授权

US07521304B1 Method for forming integrated circuit 失效
标题翻译：集成电路形成方法
公开(公告)号：US07521304B1
公开(公告)日：2009-04-21
申请号：US10230775
申请日：2002-08-29
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

75. 发明授权

US07494885B1 Disposable spacer process for field effect transistor fabrication 有权
标题翻译：场效应晶体管制造的一次性间隔工艺
公开(公告)号：US07494885B1
公开(公告)日：2009-02-24
申请号：US10818155
申请日：2004-04-05
申请人： Mario M. Pelella , Darin A. Chan , Kei-Leong Ho , Lu You
发明人： Mario M. Pelella , Darin A. Chan , Kei-Leong Ho , Lu You
IPC分类号： H01L21/00
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.
摘要翻译：根据一个示例性实施例，用于在衬底上形成场效应晶体管的方法包括形成邻近位于衬底上的栅极堆叠的一次性间隔物的步骤，其中一次性间隔物包括无定形碳。可以通过在栅极堆叠上沉积无定形碳层并且各向异性地蚀刻无定形碳层来形成一次性间隔物。该方法还包括在衬底中形成源极和漏极区域，其中源极区域和漏极区域邻近一次性间隔物定位。根据该示例性实施例，该方法还包括去除一次性间隔件，其中一次性间隔件的移除基本上不引起基板中的气刨。可以通过使用干法蚀刻工艺去除一次性间隔物。该方法还可以包括在形成一次性间隔件之前在邻近栅极堆叠的基板中形成延伸区域。

76. 发明授权

US07256499B1 Ultra low dielectric constant integrated circuit system 有权
标题翻译：超低介电常数集成电路系统
公开(公告)号：US07256499B1
公开(公告)日：2007-08-14
申请号：US11230985
申请日：2005-09-19
申请人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
发明人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.
摘要翻译：提供了一种集成电路，包括在半导体衬底上形成多孔超低介电常数介电层，并在超低介电常数介电层中形成开口。形成电介质衬垫以使开口线对，以覆盖超低介电常数电介质层中的孔，并且沉积阻挡层以对电介质衬垫进行排列，并且沉积导体芯以填充阻挡层上的开口。

77. 发明授权

US07208418B1 Sealing sidewall pores in low-k dielectrics 有权
标题翻译：密封低k电介质中的侧壁孔
公开(公告)号：US07208418B1
公开(公告)日：2007-04-24
申请号：US10728774
申请日：2003-12-08
申请人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
发明人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
IPC分类号： H01L21/311
CPC分类号： H01L21/76831
摘要： Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.
摘要翻译：通过在阻挡金属层沉积之前密封侧壁孔隙率来减少由于低k介电孔隙导致的阻挡金属层不连续性或间隙。实施例包括通过沉积溶胀剂，粘合促进剂或低k材料的附加层来密封侧壁孔隙。

78. 发明申请

US20070029604A1 Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices 审中-公开
标题翻译：使用薄的未掺杂TEOS与BPTEOS ILD或BPTEOS ILD单独改善多位存储器件中的电荷损失和接触电阻
公开(公告)号：US20070029604A1
公开(公告)日：2007-02-08
申请号：US11546688
申请日：2006-10-12
申请人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
发明人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.
摘要翻译：本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。此外，本发明包括前述的未掺杂的TEOS衬垫。

79. 发明授权

US07169706B2 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US07169706B2
公开(公告)日：2007-01-30
申请号：US10687186
申请日：2003-10-16
申请人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

80. 发明授权

US07038320B1 Single damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的单镶嵌一体化方案
公开(公告)号：US07038320B1
公开(公告)日：2006-05-02
申请号：US09785445
申请日：2001-02-20
申请人： Lu You , Fei Wang , Minh Van Ngo
发明人： Lu You , Fei Wang , Minh Van Ngo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76814 , H01L21/76834
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A second etch stop layer can also be disposed between the first diffusion barrier layer and the first etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上并与第一扩散阻挡层隔开，并且介电层设置在第一蚀刻停止层上。通孔也可以有圆角。第二蚀刻停止层也可以设置在第一扩散阻挡层和第一蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

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