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    • 77. 发明授权
    • Method of forming metal interconnection on thick polyimide film
    • 在厚聚酰亚胺膜上形成金属互连的方法
    • US08242024B2
    • 2012-08-14
    • US12562979
    • 2009-09-18
    • Chih-Chang Chen
    • Chih-Chang Chen
    • H01L21/302
    • H01L21/76816
    • Many current micromachining devices are integrated with materials such as very thick layer of polyimide (10 to 100 um) to offer essential characteristics and properties for various applications; it is inherently difficult and complicated to provide reliable metal interconnections between different levels of the circuits. The present invention is generally related to a novel micromachining process and structure to form metal interconnections in integrated circuits or micromachining devices which are incorporated with thick polyimide films. More particularly, the embodiments of the current invention relates to formation of multi-step staircase structure with tapered angle on polyimide layer, which is therefore capable of offering superb and reliable step coverage for metallization among different levels of integrated circuits, and especially for very thick polyimide layer applications.
    • 许多当前的微加工装置与诸如非常厚的聚酰亚胺(10至100μm)的材料集成,以提供用于各种应用的基本特征和性质; 在不同级别的电路之间提供可靠的金属互连本身是困难和复杂的。 本发明通常涉及一种新颖的微加工工艺和结构,以在集成电路或微加工装置中形成金属互连,其结合有聚酰亚胺厚膜。 更具体地,本发明的实施例涉及在聚酰亚胺层上形成具有锥角的多步阶梯结构,因此能够为不同级别的集成电路之间的金属化提供极好且可靠的阶梯覆盖,特别是对于非常厚的 聚酰亚胺层应用。
    • 79. 发明授权
    • Method to modify 0.25&mgr;m 1T-RAM by extra resist protect oxide (RPO) blocking
    • 通过额外的抗氧化保护氧化物(RPO)阻挡来修改0.25mum 1T-RAM的方法
    • US06528422B1
    • 2003-03-04
    • US09808924
    • 2001-03-16
    • Ching-Kwun HuangChih-Chang ChenHsien-Chih PengPin-Shyne Chin
    • Ching-Kwun HuangChih-Chang ChenHsien-Chih PengPin-Shyne Chin
    • H01L2144
    • H01L27/10873H01L27/10894
    • A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.
    • 一种制造1T-RAM设备的方法,包括以下步骤。 提供了具有接近晶体管区域和接近存取晶体管区域的电容器区域内的暴露底板的半导体衬底。 在存取晶体管区域内形成具有底层栅介质层的栅极。 栅极和底层栅介质层具有形成在它们各自暴露的侧壁上的侧壁间隔物。 形成在电容器区域内的底板上方具有底层电容器层的顶板。 顶板和底层电容器层具有形成在它们各自的暴露的侧壁上的侧壁间隔物。 形成图案化的抗蚀剂保护氧化物(RPO)层至少在不被硅化的结构的漏极上。 在不受RPO层保护的结构上形成金属硅化物部分。