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71. 发明授权

US5802336A Microprocessor capable of unpacking packed data 失效
标题翻译：能够解包打包数据的微处理器
公开(公告)号：US5802336A
公开(公告)日：1998-09-01
申请号：US791003
申请日：1997-01-27
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30 , G06F9/302 , G06F9/315 , G06F9/318
CPC分类号： G06F9/30036 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30196 , G06F7/49921
摘要： A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
摘要翻译：处理器处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。解码器具有控制信号输入。控制信号输入用于接收第一控制信号和第二控制信号。第一控制信号用于指示包装操作。第二控制信号用于指示解封装操作。功能单元耦合到解码器和寄存器。功能单元用于使用第一打包数据执行包操作和拆包操作。处理器还支持移动操作。

72. 发明申请

US20130124831A1 Method and Apparatus for Packing Packed Data 审中-公开
公开(公告)号：US20130124831A1
公开(公告)日：2013-05-16
申请号：US13730842
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benney Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benney Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

73. 发明申请

US20130124830A1 Method and Apparatus for Unpacking Packed Data 审中-公开
标题翻译：打包数据的方法和装置
公开(公告)号：US20130124830A1
公开(公告)日：2013-05-16
申请号：US13730841
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benney Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benney Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。从第一源寄存器接收第一打包数据元素和第三打包数据元素。从第二源寄存器接收第二打包数据元素和第四打包数据元素。所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素数据元素。

74. 发明授权

US5822232A Method for performing box filter 失效
标题翻译：执行箱式过滤器的方法
公开(公告)号：US5822232A
公开(公告)日：1998-10-13
申请号：US609601
申请日：1996-03-01
申请人： Carole Dulong , Mike Kelly , Larry M. Mennemeier
发明人： Carole Dulong , Mike Kelly , Larry M. Mennemeier
IPC分类号： G06F17/10
CPC分类号： G06F17/10
摘要： A computer implemented method for box filtering an array of data. The method includes a first step of filtering the rows of an array. The rows are in packed data sequences, each sequence having a plurality of packed data elements. Each row is filtered by generating copies of the row, aligning the copies, and generating a sum of the copies. The sum is generated by simultaneously adding corresponding packed elements of two rows in response to executing a first instruction. The columns of the array are filtered by sequentially adding, in response to executing the first instruction, filtered rows to a preceding and succeeding filtered row.
摘要翻译：一种用于对数据数组进行盒子过滤的计算机实现方法。该方法包括对阵列的行进行过滤的第一步骤。这些行是打包数据序列，每个序列具有多个打包数据元素。通过生成行的副本，对齐副本以及生成副本的总和来对每行进行过滤。通过响应于执行第一指令同时添加两行的相应的打包元素来生成和。通过将执行第一条指令的过滤行顺序地添加到前一个和后续的过滤行中，对数组的列进行过滤。

75. 发明申请

US20130124832A1 Method and Apparatus for Unpacking Packed Data 审中-公开
公开(公告)号：US20130124832A1
公开(公告)日：2013-05-16
申请号：US13730845
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benney Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benney Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

76. 发明授权

US5742529A Method and an apparatus for providing the absolute difference of unsigned values 失效
标题翻译：用于提供无符号值的绝对差的方法和装置
公开(公告)号：US5742529A
公开(公告)日：1998-04-21
申请号：US576129
申请日：1995-12-21
申请人： Larry M. Mennemeier , Alexander D. Peleg , Coby Gottlieb
发明人： Larry M. Mennemeier , Alexander D. Peleg , Coby Gottlieb
IPC分类号： G06F7/544 , G06F7/00 , G06F7/38
CPC分类号： G06F7/544 , G06F17/10 , G06F2207/3828 , G06F2207/5442 , G06F7/49921
摘要： In a computer system storing a first packed data and a second packed data having corresponding data elements where the data elements representing unsigned values having a method for determining the absolute difference of the corresponding data elements. The method comprising the steps of subtracting with saturation the data elements in the first packed data from the corresponding data elements in the second packed data to generate a third packed data in response to a first instruction, subtracting with saturation the data elements in the second packed data from the corresponding data elements in the first packed data to generate a fourth packed data in response to a second instruction and performing an operation to select the data elements of the third packed data and the fourth packed data of greatest value to generate a fifth packed data in response to a third instruction.
摘要翻译：在存储第一打包数据的计算机系统和具有相应数据元素的第二打包数据中，其中表示无符号值的数据元素具有用于确定相应数据元素的绝对差的方法。该方法包括以下步骤：从第二打包数据中的相应数据元素饱和地减去第一打包数据中的数据元素，以响应于第一指令产生第三打包数据，以饱和度减去第二打包数据中的数据元素来自第一打包数据中的相应数据元素的数据，以响应于第二指令生成第四打包数据，并且执行选择第三打包数据的数据元素和最大值的第四打包数据的操作以生成第五打包响应于第三条指令的数据。

77. 发明授权

US5880979A System for providing the absolute difference of unsigned values 失效
标题翻译：用于提供无符号值的绝对差的系统
公开(公告)号：US5880979A
公开(公告)日：1999-03-09
申请号：US576469
申请日：1995-12-21
申请人： Larry M. Mennemeier , Alexander D. Peleg , Koby Gottlieb
发明人： Larry M. Mennemeier , Alexander D. Peleg , Koby Gottlieb
IPC分类号： G06F7/544 , G06F9/302 , G06F7/00 , G06F7/38
CPC分类号： G06F9/30014 , G06F17/10 , G06F7/544 , G06F9/30036 , G06F2207/5442
摘要： In a computer system storing a first packed data and a second packed data having corresponding data elements where the data elements representing unsigned values having a system for determining the absolute difference of the corresponding data elements. The system comprising the steps of subtracting with saturation the data elements in the first packed data from the corresponding data elements in the second packed data to generate a third packed data in response to a first instruction, subtracting with saturation the data elements in the second packed data from the corresponding data elements in the first packed data to generate a fourth packed data in response to a second instruction and performing an operation to select the data elements of the third packed data and the fourth packed data of greatest value to generate a fifth packed data in response to a third instruction.
摘要翻译：在存储第一打包数据的计算机系统和具有相应数据元素的第二打包数据中，其中表示无符号值的数据元素具有用于确定相应数据元素的绝对差的系统。该系统包括以下步骤：饱和地从第二打包数据中的相应数据元素中减去第一打包数据中的数据元素，以响应于第一指令产生第三打包数据，以饱和度减去第二打包数据中的数据元素来自第一打包数据中的相应数据元素的数据，以响应于第二指令生成第四打包数据，并且执行选择第三打包数据的数据元素和最大值的第四打包数据的操作以生成第五打包响应于第三条指令的数据。

78. 发明授权

US5862067A Method and apparatus for providing high numerical accuracy with packed multiply-add or multiply-subtract operations 失效
标题翻译：用多重加法或多重乘法运算提供高数值精度的方法和装置
公开(公告)号：US5862067A
公开(公告)日：1999-01-19
申请号：US581067
申请日：1995-12-29
申请人： Larry M. Mennemeier , David I-Keong Wong
发明人： Larry M. Mennemeier , David I-Keong Wong
IPC分类号： G06F7/544 , G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3828
摘要： A method and apparatus for combining at least two packed multiply-accumulate instructions (or equivalent operations) to compute a filter result from coefficients having more bits than can be processed by a single multiply-accumulate instruction (or equivalent operation). This achieves greater accuracy in computing transforms and digital filters without requiring more expensive hardware to implement multiply-accumulate instructions for larger operands. Typical applications are compression/decompression algorithms, modem, audio and video. The invention is scalable, permitting additional multiply-accumulate instructions to be added as incrementally larger coefficients are required. Additionally, the invention permits different numbers of multiply-accumulate instructions for each coefficient depending on the sensitivity to that particular coefficient.
摘要翻译：一种用于组合至少两个压缩乘法累加指令（或等效操作）以从具有比可由单次乘法累加指令（或等效操作）处理的比特多的比特的系数计算滤波器结果的方法和装置。这在计算变换和数字滤波器方面实现更高的精度，而不需要更昂贵的硬件来实现较大操作数的乘法累加指令。典型的应用是压缩/解压缩算法，调制解调器，音频和视频。本发明是可扩展的，允许附加的乘法累积指令被添加为需要递增更大的系数。此外，根据对该特定系数的敏感度，本发明允许针对每个系数的不同数量的乘法累加指令。

79. 发明授权

US5831885A Computer implemented method for performing division emulation 失效
标题翻译：用于执行分割仿真的计算机实现方法
公开(公告)号：US5831885A
公开(公告)日：1998-11-03
申请号：US610701
申请日：1996-03-04
申请人： Larry M. Mennemeier
发明人： Larry M. Mennemeier
IPC分类号： G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/3828 , G06F2207/5355 , G06F2207/5356 , G06F7/49936
摘要： A computer implemented method for generating a quotient. The method is exclusive of division operations. The method includes a first step of generating, in response to a first instruction, a first delta by performing an operation between a denominator and a first value. A second step of generating, in response to a second instruction, a second delta by performing an operation between the denominator and the first delta. A third step of generating, in response to the second instruction, a third delta by performing an operation between the second delta and the denominator. A fourth step of joining, in response to a fourth instruction, the third delta to the first delta. Repeating the first through fourth steps until the first delta is equal to a predetermined value. Generating the quotient, in response to a fifth instruction, by performing an operation between the first delta and a numerator.
摘要翻译：一种用于生成商的计算机实现方法。该方法不包括除法运算。该方法包括：通过执行分母和第一值之间的操作，响应于第一指令而产生第一增量的第一步骤。通过执行分母和第一增量之间的操作，响应于第二指令产生第二增量的第二步骤。通过执行第二增量和分母之间的操作，响应于第二指令产生第三增量的第三步骤。第四步骤，响应于第四指令将第三增量加到第一增量。重复第一到第四步骤，直到第一增量等于预定值。响应于第五指令，通过执行第一增量和分子之间的操作来生成商。

80. 发明授权

US5642306A Method and apparatus for a single instruction multiple data early-out zero-skip multiplier 失效
标题翻译：单指令多数据提前零跳过乘数的方法和装置
公开(公告)号：US5642306A
公开(公告)日：1997-06-24
申请号：US645633
申请日：1996-05-15
申请人： Larry M. Mennemeier , Wolf C. Witt
发明人： Larry M. Mennemeier , Wolf C. Witt
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/523 , G06F2207/3828
摘要： A method and apparatus for multiple parallel multiplications of multiple packed data using a single multiplier is provided. Given multiple packed data as multiplicand blocks and as multiplier blocks, an early-out zero-skip feature examines a multiplicand block to be multiplied to determine if the multiplicand block consists of all zeros. If the multiplicand block consists of all zeros, then the corresponding multiplication is skipped. The early-out zero skip multiplier also examines the most significant bits of a multiplier block to be multiplied to determine if the most significant bits consist of all zeros. If the most significant bits of the multiplier block to be multiplied consist of all zeros, then the multiplicand block is multiplied with only the least significant bits of the corresponding multiplier block. Otherwise, if the most significant bits of the multiplier block consist of both zeros and ones, then the corresponding multiplicand block is multiplied with the entire multiplier block.
摘要翻译：提供了使用单个乘法器对多个打包数据进行多次并行乘法的方法和装置。给定多个打包数据作为被乘数块和乘数块，早期的零跳跃特征检查要乘以的被乘数块以确定被乘数块是否由全零组成。如果被乘数块由全零组成，则跳过相应的乘法。早期的零跳过乘数还检查要乘以的乘法器块的最高有效位，以确定最高有效位是否由全零组成。如果要乘法乘法器块的最高有效位由全零组成，则被乘数块仅与相应乘法器块的最低有效位相乘。否则，如果乘法器块的最高有效位由零和1组成，则相应的被乘数块与整个乘法器块相乘。

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