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71. 发明申请

US20110044121A1 SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER 审中-公开
标题翻译：具有用于控制位线负载的设备的半导体存储器件和提高位线感测放大器的感测效率
公开(公告)号：US20110044121A1
公开(公告)日：2011-02-24
申请号：US12860484
申请日：2010-08-20
申请人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
发明人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
IPC分类号： G11C7/06
CPC分类号： G11C11/4094 , G11C11/4091 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.
摘要翻译：半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器，读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块。

72. 发明申请

US20100226192A1 Semiconductor memory device having improved local input/output line precharge scheme 有权
标题翻译：具有改进的本地输入/输出线预充电方案的半导体存储器件
公开(公告)号：US20100226192A1
公开(公告)日：2010-09-09
申请号：US12659328
申请日：2010-03-04
申请人： Jong-Ho Moon , Seong-Jin Jang
发明人： Jong-Ho Moon , Seong-Jin Jang
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C11/4096
摘要： A data path circuit of a semiconductor memory device includes: a bit line sense amplifier driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit operatively connecting a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and a local input/output line precharge unit precharging the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state.
摘要翻译：半导体存储器件的数据路径电路包括：由第一电源电压驱动的位线读出放大器; 本地输入/输出线路读出放大器; 列选择单元，可操作地连接连接到位线读出放大器的一对位线和响应于列选择信号连接到本地输入/输出线读出放大器的一对本地输入/输出线; 以及本地输入/输出线预充电单元，在列选择信号处于非活动状态的期间，用与第一电源电压不同的第二电源电压对一对本地输入/输出线进行预充电。

73. 发明授权

US07733715B2 Memory system, memory device, and output data strobe signal generating method 失效
标题翻译：存储器系统，存储器件和输出数据选通信号生成方法
公开(公告)号：US07733715B2
公开(公告)日：2010-06-08
申请号：US12071347
申请日：2008-02-20
申请人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.
摘要翻译：输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导码信号。

74. 发明授权

US07499341B2 Output circuit, semiconductor memory device having the same, and method of expanding a valid output data window 有权
标题翻译：输出电路，具有相同的半导体存储器件以及扩展有效输出数据窗口的方法
公开(公告)号：US07499341B2
公开(公告)日：2009-03-03
申请号：US11601027
申请日：2006-11-17
申请人： Woo-Jin Lee , Hyun-Dong Kim , Seong-Jin Jang
发明人： Woo-Jin Lee , Hyun-Dong Kim , Seong-Jin Jang
IPC分类号： G11C7/10
CPC分类号： G11C29/48 , G11C7/1051 , G11C7/1069 , G11C29/1201 , G11C29/12015 , G11C29/14
摘要： A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.
摘要翻译：描述半导体存储器件和扩展有效输出数据窗口的方法。半导体存储器件包括存储单元阵列和输出电路。存储单元阵列产生具有多个位的读取数据。输出电路响应于正常模式下的时钟信号顺序地输出读取的数据。另一方面，输出电路通过在读取数据的比特之间锁存待测试的比特来选择性地输出读取的数据的比特，并且响应于多个读取数据，通过电连接在读取的数据的比特之间的不被测试的比特在测试模式下切换控制信号。因此，可以扩展输出数据的有效数据窗口。

75. 发明申请

US20080291753A1 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US20080291753A1
公开(公告)日：2008-11-27
申请号：US12219816
申请日：2008-07-29
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

76. 发明授权

US07453745B2 Semiconductor memory device and latency signal generating method thereof 有权
公开(公告)号：US07453745B2
公开(公告)日：2008-11-18
申请号：US11416077
申请日：2006-05-03
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

77. 发明授权

US07420387B2 Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device 有权
标题翻译：能够控制OCD和ODT电路的半导体器件和半导体器件使用的控制方法
公开(公告)号：US07420387B2
公开(公告)日：2008-09-02
申请号：US11402123
申请日：2006-04-11
申请人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim , Seong-Jin Jang
发明人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim , Seong-Jin Jang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.
摘要翻译：提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗根据调整后的控制代码进行调整。半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。因此，可以更精确地调整OCD电路或ODT电路的阻抗。

78. 发明授权

US07394720B2 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
标题翻译：在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US07394720B2
公开(公告)日：2008-07-01
申请号：US11560746
申请日：2006-11-16
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

79. 发明授权

US07376041B2 Semiconductor memory device and data read and write method of the same 失效
标题翻译：半导体存储器件和数据读写方法相同
公开(公告)号：US07376041B2
公开(公告)日：2008-05-20
申请号：US11024272
申请日：2004-12-27
申请人： Seong-Jin Jang
发明人： Seong-Jin Jang
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/22 , G11C7/1066
摘要： A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.
摘要翻译：半导体存储器件包括用于存储数据的存储单元阵列; 数据输入部分，用于响应写控制信号将数据输出到存储单元阵列; 数据输出部分，用于响应于读取控制信号从存储单元阵列输出数据; 数据I / O门，用于响应于写控制信号将从数据输入部分输出的数据发送到存储单元阵列;以及响应于读控制信号将从存储单元阵列输出的数据发送到数据输出部分; 以及数据I / O控制器，用于产生具有比所读取的控制信号的最小周期时间更小的最小周期时间的读取控制信号和写入控制信号。与在可操作频率范围内具有低工作频率的半导体存储器件相比，具有改进的操作性能。

80. 发明授权

US07366822B2 Semiconductor memory device capable of reading and writing data at the same time 有权
标题翻译：能够同时读取和写入数据的半导体存储器件
公开(公告)号：US07366822B2
公开(公告)日：2008-04-29
申请号：US10840268
申请日：2004-05-07
申请人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
发明人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C11/4082 , G11C11/4087
摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.
摘要翻译：半导体存储器件包括多个存储体。数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少。

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