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    • 76. 发明授权
    • Asymmetric differential inductor
    • 不对称差分电感
    • US08493168B2
    • 2013-07-23
    • US13222231
    • 2011-08-31
    • Ming-Fan TsaiKuan-Yu ChenBo-Shiang FangHsin-Hung Lee
    • Ming-Fan TsaiKuan-Yu ChenBo-Shiang FangHsin-Hung Lee
    • H01F5/00H01F27/28
    • H01F17/0006H01F19/00
    • An asymmetric differential inductor includes first and second conductive wirings spirally disposed on a substrate having a first input terminal, a second input terminal, a ground terminal, and a central conductive wiring. The central conductive wiring has a central contact connecting the ground terminal and a central end away from the ground terminal. The first conductive wiring extends across the central conductive wiring and has a first contact connecting the first input terminal and a first end connecting the central end. The second conductive wiring extends across the central conductive wiring and interlaces with the first conductive wiring and has a second contact connecting the second input terminal and a second end connecting the central end. Corresponding portions of wiring sections of the first and second conductive wirings at opposite sides of the central conductive wiring are asymmetrical to one another to thereby save substrate space and facilitate circuit layout.
    • 非对称差分电感器包括螺旋地设置在具有第一输入端子,第二输入端子,接地端子和中心导电布线的基板上的第一和第二导电布线。 中心导电布线具有连接接地端子和远离接地端子的中心端的中心接触点。 第一导电布线延伸穿过中心导电布线,并且具有连接第一输入端和连接中心端的第一端的第一触点。 所述第二导电布线延伸穿过所述中心导电布线并与所述第一导电布线交织,并且具有连接所述第二输入端子和连接所述中心端部的第二端部的第二触点。 在中心导电布线的相对侧的第一和第二导电布线的布线部分的相应部分彼此不对称,从而节省基板空间并且便于布线。
    • 79. 发明授权
    • Symmetric differential inductor structure
    • 对称差分电感结构
    • US08305182B1
    • 2012-11-06
    • US13243138
    • 2011-09-23
    • Ming-Fan TsaiKuan-Yu ChenBo-Shiang FangHsin-Hung Lee
    • Ming-Fan TsaiKuan-Yu ChenBo-Shiang FangHsin-Hung Lee
    • H01F5/00H01F27/28
    • H01L23/5227H01F19/04H01L2924/0002H01L2924/00
    • A symmetric differential inductor structure includes first, second, third and fourth spiral conductive wirings disposed in four quadrants of a substrate, respectively. Further, a fifth conductive wiring connects the first and fourth spiral conductive wirings, and a sixth conductive wiring connects the second and third spiral conductive wirings. The first and second spiral conductive wirings are symmetric but not intersected with one another, and the third and fourth spiral conductive wirings are symmetric but not intersected with one another. Therefore, the invention attains full geometric symmetry to avoid using conductive wirings that occupy a large area of the substrate as in the prior art and to thereby increase the product profit and yield.
    • 对称差分电感器结构包括分别设置在基板的四个象限内的第一,第二,第三和第四螺旋导电布线。 此外,第五导电布线连接第一和第四螺旋导电布线,并且第六导电布线连接第二和第三螺旋导电布线。 第一和第二螺旋导电布线是对称的,但是彼此不相交,第三和第四螺旋导电布线是对称的但彼此不相交。 因此,本发明获得完全的几何对称性,以避免如现有技术那样使用占据基板的大面积的导电布线,从而提高产品利润和产量。
    • 80. 发明申请
    • TRANSISTOR ARRAY SUBSTRATE
    • 晶体管阵列基板
    • US20120248431A1
    • 2012-10-04
    • US13183838
    • 2011-07-15
    • Ya-Huei HUANGKuan-Yu ChenYing-Hui ChenTe-Yu Chen
    • Ya-Huei HUANGKuan-Yu ChenYing-Hui ChenTe-Yu Chen
    • H01L29/786
    • H01L27/1225
    • A transistor array substrate includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units. The scan lines and the data lines are all disposed on the substrate. Each pixel unit includes a transistor and a pixel electrode. The transistor is electrically connected to the pixel electrodes, the scan lines and the data lines. Each transistor includes a gate, a drain, a source, a metal-oxide-semiconductor layer and a channel protective layer. A channel gap exists between the drain and the source. The metal-oxide-semiconductor layer has a pair of side edges opposite to each other and the side edges are located at two ends of the channel gap. The channel protective layer covers the metal-oxide-semiconductor layer in the channel gap and protrudes from the side edges of the metal-oxide-semiconductor layer.
    • 晶体管阵列基板包括基板,多条扫描线,多条数据线和多个像素单元。 扫描线和数据线都设置在基板上。 每个像素单元包括晶体管和像素电极。 晶体管电连接到像素电极,扫描线和数据线。 每个晶体管包括栅极,漏极,源极,金属氧化物半导体层和沟道保护层。 漏极和源极之间存在沟道间隙。 金属氧化物半导体层具有彼此相对的一对侧边缘,并且侧边缘位于沟道间隙的两端。 沟道保护层覆盖沟道间隙中的金属氧化物半导体层,并从金属氧化物半导体层的侧边缘突出。