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71. 发明授权

US07440511B2 Transmit filter 有权
标题翻译：发射滤波器
公开(公告)号：US07440511B2
公开(公告)日：2008-10-21
申请号：US10001448
申请日：2001-10-31
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H04L27/00
CPC分类号： H03H17/0283 , H04L7/0029
摘要： A transmit filter (100) receives a stream of data symbols (DT_TX) at a baseband symbol clock rate. An available clock (FREF) is used to generate sample points for producing a generating an oversampled signal. The available clock is independent from the baseband symbol clock, and does not need to be an integer multiple of the clock. Upon identifying a start sequence in the data stream, a phase tracking circuit (106) is used to determine a current position relative to the baseband symbol clock. A state circuit (104) stores the last three, or more, data symbols. Based on the last three data symbols (which determines the shape of the curve for the current data symbol) and the current position (which determines the current position on the curve), a filter circuit (108) generates a sample point.
摘要翻译：发射滤波器（100）以基带符号时钟速率接收数据符号流（DT_TX）。可用时钟（FREF）用于产生用于产生过采样信号的采样点。可用时钟独立于基带符号时钟，不需要是时钟的整数倍。在识别数据流中的起始序列时，使用相位跟踪电路（106）来确定相对于基带符号时钟的当前位置。状态电路（104）存储最后三个或更多数据符号。基于最后三个数据符号（其确定当前数据符号的曲线的形状）和当前位置（其确定曲线上的当前位置），滤波器电路（108）产生采样点。

72. 发明申请

US20080157839A1 TIME-TO-DIGITAL CONVERTER WITH NON-INVERTING BUFFERS, TRANSMISSION GATES AND NON-LINEARITY CORRECTOR, SOC INCLUDING SUCH CONVERTER AND METHOD OF PHASE DETECTION FOR USE IN SYNTHESIZING A CLOCK SIGNAL 有权
标题翻译：具有非反相缓冲器，传输门和非线性校正器的时间到数字转换器，包括这种转换器的SOC以及用于合成时钟信号的相位检测方法
公开(公告)号：US20080157839A1
公开(公告)日：2008-07-03
申请号：US11690506
申请日：2007-03-23
申请人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
发明人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H03L2207/50
摘要： A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.
摘要翻译：时间数字转换器（TDC），包括TDC的片上系统，用于合成时钟信号的相位检测方法和用于TDC的非线性校正器。在一个实施例中，TDC包括被配置为接收时钟信号并产生延迟的时钟信号的延迟元件链。每个延迟元件包括：（1）非反相缓冲器，被配置为将时钟信号延迟约两倍的逆变器的延迟以提供缓冲器延迟的时钟信号，以及（2）耦合到非反相缓冲器的第一传输门反相缓冲器并且被配置为将时钟信号延迟大约逆变器的延迟以提供第一门延迟的时钟信号。

73. 发明授权

US07375598B2 System and method for increasing radio frequency (RF)/microwave inductor-capacitor (LC) oscillator frequency tuning range 有权
标题翻译：提高射频（RF）/微波电感 - 电容（LC）振荡器频率调谐范围的系统和方法
公开(公告)号：US07375598B2
公开(公告)日：2008-05-20
申请号：US11009495
申请日：2004-12-10
申请人： Chih-Ming Hung , Dirk Leipold , Nathen Barton
发明人： Chih-Ming Hung , Dirk Leipold , Nathen Barton
IPC分类号： H03B5/00
CPC分类号： H03B5/1296 , H03B5/1209 , H03B5/1256 , H03B5/1287
摘要： System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. A preferred embodiment comprises a voltage controlled oscillator (VCO) configured to generate an output signal at a frequency that is dependent upon a magnitude of an input voltage level and an effective inductance of an inductive load and a variable inductor coupled to the VCO. The variable inductor comprises a primary inductor coupled to the VCO to produce a magnetic field based upon a current flowing through the primary inductor and a secondary inductor magnetically coupled to the primary inductor, the secondary inductor to affect the magnitude of the effective inductance of the primary inductor.
摘要翻译：用于增加RF /微波LC振荡器的频率调谐范围的系统和方法。优选实施例包括压控振荡器（VCO），其被配置为以取决于输入电压电平的大小和耦合到VCO的电感性负载和可变电感器的有效电感的频率来产生输出信号。可变电感器包括耦合到VCO的初级电感器，以基于流过初级电感器的电流和与主电感器磁耦合的次级电感器产生磁场，次级电感器影响主电感器的有效电感的幅度电感。

74. 发明授权

US07183860B2 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US07183860B2
公开(公告)日：2007-02-27
申请号：US11149859
申请日：2005-06-10
申请人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
发明人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
IPC分类号： H03C3/06 , H03L7/091 , H03L7/099
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

75. 发明申请

US20050287967A1 Low noise high isolation transmit buffer gain control mechanism 有权
标题翻译：低噪声高隔离传输缓冲器增益控制机制
公开(公告)号：US20050287967A1
公开(公告)日：2005-12-29
申请号：US11115815
申请日：2005-04-26
申请人： Chih-Ming Hung , Francis Cruise , Dirk Leipold , Robert Staszewski
发明人： Chih-Ming Hung , Francis Cruise , Dirk Leipold , Robert Staszewski
IPC分类号： H01Q11/12 , H03F1/32 , H03F3/191 , H04B1/04
CPC分类号： H04B1/0483 , H03F1/3241 , H03F1/3294 , H03F3/191 , H03F2200/331
摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
摘要翻译：一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。发送缓冲器构造为NMOS开关阵列。每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

76. 发明授权

US06809598B1 Hybrid of predictive and closed-loop phase-domain digital PLL architecture 有权
标题翻译：预测和闭环相域数字PLL架构的混合
公开(公告)号：US06809598B1
公开(公告)日：2004-10-26
申请号：US09695516
申请日：2000-10-24
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth Maggio
IPC分类号： H03L706
CPC分类号： H04B1/7156 , H03C3/0925 , H03C3/0941 , H03C3/0966 , H03C3/0975 , H03L7/1806 , H03L2207/50 , H04B2001/71566 , H04L27/12
摘要： A phase-domain digital PLL loop is implemented using a hybrid of predictive and closed-loop architecture that allows direct DCO oscillator transmit modulation in the GFSK modulation scheme of “BLUETOOTH” or GSM, as well as the chip phase modulation of the 802.11b or Wideband-CDMA. The current gain of the DCO oscillator is predicted by observing past phase error responses to previous DCO corrections. DCO control is then augmented with the “open-loop” instantaneous frequency jump estimate of the new frequency control word.
摘要翻译：使用预测和闭环架构的混合来实现相域数字PLL环路，其允许在“蓝牙”或GSM的GFSK调制方案中直接DCO振荡器发送调制，以及802.11b的芯片相位调制或宽带CDMA。 DCO振荡器的当前增益是通过观察对先前DCO校正的过去相位误差响应来预测的。然后用新的频率控制字的“开环”瞬时频率跳跃估计来增加DCO控制。

77. 发明授权

US06593773B2 Power saving circuitry using predictive logic 有权
公开(公告)号：US06593773B2
公开(公告)日：2003-07-15
申请号：US09967275
申请日：2001-09-28
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D324
CPC分类号： H03L7/16 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L2207/50 , H04L7/0029
摘要： To conserve power in a circuit where a high-speed signal HSIG controls combinational logic (10), while a low-speed signal LCLK drives a logic/memory circuit (12) that samples the output of the combinational logic, predictive logic state machine (14) generates a clock, P_LCLK, which has an active level preceding the active edge of LCLK by a period sufficient to allow the combinational logic to reach the desired state prior to the active edge of LCLK and, preferably, allows for possible jitter in LCLK. Responsive to P_LCLK, the signal suspend circuitry (16) either passes HSIG or gates off HSIG. Further reductions in power can be accomplished by predicting which portions of the logic/memory circuit (12) will be used, and clocking those portions.

78. 发明授权

US06326851B1 Digital phase-domain PLL frequency synthesizer 有权
标题翻译：数字相域PLL频率合成器
公开(公告)号：US06326851B1
公开(公告)日：2001-12-04
申请号：US09603023
申请日：2000-06-26
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03L7085
CPC分类号： H03L7/18 , H03L7/085
摘要： A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.
摘要翻译：频率合成器架构自然地将发射机调制能力与宽带全数字PLL调制方案相结合，以通过在同步相域中操作来最大化数字密集型实现。通过实施与参考计算相关联的定时调整，跨数字控制VCO提供同步逻辑，并且与VCO输出时钟同步，以允许频率控制字包含信道信息和发送调制信息。

79. 发明授权

US08385476B2 Digital phase locked loop 有权
公开(公告)号：US08385476B2
公开(公告)日：2013-02-26
申请号：US10131523
申请日：2002-04-24
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H03L7/0992 , H03C3/0966 , H03K19/0016 , H03L7/08 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/0991 , H03L7/16 , H03L2207/50 , H04L7/0029 , H04L7/0331
摘要： A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

80. 发明授权

US08284886B2 Radio frequency built-in self test for quality monitoring of local oscillator and transmitter 有权
标题翻译：射频内置自检，用于本地振荡器和发射机的质量监控
公开(公告)号：US08284886B2
公开(公告)日：2012-10-09
申请号：US10758863
申请日：2004-01-16
申请人： Robert B. Staszewski , Dirk Leipold , Elida de-Obaldia
发明人： Robert B. Staszewski , Dirk Leipold , Elida de-Obaldia
IPC分类号： H03D3/24
CPC分类号： G01R31/2822 , G01R31/2824 , G01R31/3187 , H03L7/085 , H03L7/095 , H03L2207/50 , H04B17/19
摘要： A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment comprises observing a digital signal from within an RF circuit, manipulating the signal with digital signal processing techniques, and determining if the RF circuit passes a test based upon results from the manipulating. Since the signal is clocked at a much lower frequency than an RF output of the RF circuit and the manipulation is performed digitally, testing can be performed at different stages of the production cycle and expensive test equipment can be eliminated.
摘要翻译：用于无线RF应用的本地振荡器和发射机的低成本性能和一致性测试的系统和方法。优选实施例包括观察来自RF电路内的数字信号，用数字信号处理技术操纵信号，以及基于来自操作的结果来确定RF电路是否通过测试。由于该信号以比RF电路的RF输出低得多的频率进行计时，并且数字地执行操作，所以可以在生产周期的不同阶段执行测试，并且可以消除昂贵的测试设备。

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