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71. 发明授权

US07116135B2 Programmable high speed I/O interface 有权
公开(公告)号：US07116135B2
公开(公告)日：2006-10-03
申请号：US10886015
申请日：2004-07-06
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

72. 发明授权

US07030675B1 Apparatus and method for controlling a delay chain 失效
标题翻译：用于控制延迟链的装置和方法
公开(公告)号：US07030675B1
公开(公告)日：2006-04-18
申请号：US10932642
申请日：2004-08-31
申请人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Yan Chong , Khai Nguyen , Henry Kim
发明人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Yan Chong , Khai Nguyen , Henry Kim
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K5/1252 , H03L7/0805 , H03L7/0814
摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.
摘要翻译：一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。寄存器用于调节到延迟链的控制信号。当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

73. 发明授权

US06825698B2 Programmable high speed I/O interface 有权
标题翻译：可编程高速I / O接口
公开(公告)号：US06825698B2
公开(公告)日：2004-11-30
申请号：US10229342
申请日：2002-08-26
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B100
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

74. 发明授权

US07200769B1 Self-compensating delay chain for multiple-date-rate interfaces 有权
标题翻译：多速率接口的自补偿延迟链
公开(公告)号：US07200769B1
公开(公告)日：2007-04-03
申请号：US10037861
申请日：2002-01-02
申请人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
发明人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
IPC分类号： G06F1/04
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/108 , H03L7/0805 , H03L7/0814 , H03L7/091
摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
摘要翻译：用于延迟多数据速率接口的时钟信号的方法和装置。一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

75. 发明授权

US07725755B1 Self-compensating delay chain for multiple-date-rate interfaces 有权
标题翻译：多速率接口的自补偿延迟链
公开(公告)号：US07725755B1
公开(公告)日：2010-05-25
申请号：US11668353
申请日：2007-01-29
申请人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
发明人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
IPC分类号： G06F1/00 , G06F1/14
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/108 , H03L7/0805 , H03L7/0814 , H03L7/091
摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
摘要翻译：用于延迟多数据速率接口的时钟信号的方法和装置。一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

76. 发明授权

US08400186B1 Techniques for buffering single-ended and differential signals 有权
标题翻译：用于缓冲单端和差分信号的技术
公开(公告)号：US08400186B1
公开(公告)日：2013-03-19
申请号：US13401562
申请日：2012-02-21
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
IPC分类号： H03K19/094
CPC分类号： H03K19/018578
摘要： A circuit comprises first and second differential pairs and first and second switch circuits. The first differential pair includes first and second transistors operable to generate a first output signal based on a first input signal in a single-ended mode. The second differential pair includes third and fourth transistors operable to generate a second output signal based on a second input signal in the single-ended mode. The first switch circuit is operable to block current through the second transistor in a differential mode. The second switch circuit is operable to block current through the third transistor in the differential mode. The first and the fourth transistors are operable to generate a third output signal based on a third input signal in the differential mode.
摘要翻译：电路包括第一和第二差分对以及第一和第二开关电路。第一差分对包括可操作以基于单端模式中的第一输入信号产生第一输出信号的第一和第二晶体管。第二差分对包括第三和第四晶体管，其可操作以基于单端模式中的第二输入信号产生第二输出信号。第一开关电路可操作以在差分模式下阻断通过第二晶体管的电流。第二开关电路可操作以在差分模式下阻断通过第三晶体管的电流。第一和第四晶体管可操作以基于差分模式中的第三输入信号产生第三输出信号。

77. 发明申请

US20050253626A1 Supply voltage detection circuit 有权
公开(公告)号：US20050253626A1
公开(公告)日：2005-11-17
申请号：US11005890
申请日：2004-12-06
申请人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In What Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Shumarayev , Thomas White
发明人： Yan Chong , Chiakang Sung , Bonnie Wang , Khai Nguyen , Joseph Huang , Xiaobao Wang , Philip Pan , In What Kim , Gopi Rangan , Tzung-Chin Chang , Surgey Shumarayev , Thomas White
IPC分类号： G01R19/155 , G06F1/24 , G06F1/28 , G06F1/32 , H03K3/356 , H03K17/22 , H03K19/0175
CPC分类号： H03K3/356008 , G01R19/155 , G06F1/24 , G06F1/28 , G06F1/3203 , H03K17/223
摘要： A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

78. 发明授权

US06538469B1 Technique to test an integrated circuit using fewer pins 有权
标题翻译：使用较少引脚测试集成电路的技术
公开(公告)号：US06538469B1
公开(公告)日：2003-03-25
申请号：US09630071
申请日：2000-07-31
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Xiaobao Wang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Xiaobao Wang
IPC分类号： H03K19177
CPC分类号： H03K19/17764 , G01R31/318516 , G01R31/318555 , G06F11/2273 , H03K19/17744
摘要： A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a package with fewer pins. This technique may be used to implement test Functions in a programmable logic device. Test data may be serially input using a test pin (410) for two or more columns (320) of logic blocks. The test data is stored in an A resister (330), and may be later transferred into a B register (335).
摘要翻译：实现需要较少的集成电路引脚的功能以将数据串行传输到用于多个逻辑块的集成电路的技术。通过减少所需的引脚，可以将集成电路下降到具有较少引脚的封装中。该技术可用于在可编程逻辑器件中实现测试功能。可以使用针对逻辑块的两列或多列（320）的测试引脚（410）来串行输入测试数据。测试数据存储在A寄存器（330）中，并且可以稍后传送到B寄存器（335）。

79. 发明授权

US08390315B1 Configurable input-output (I/O) circuitry with pre-emphasis circuitry 有权
标题翻译：具有预加重电路的可组态输入输出（I / O）电路
公开(公告)号：US08390315B1
公开(公告)日：2013-03-05
申请号：US13354780
申请日：2012-01-20
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
IPC分类号： H03K19/013 , H03K17/16
CPC分类号： H03K19/01721 , H03K19/018571
摘要： Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.
摘要翻译：公开了具有可配置的输入 - 输出电路来操作集成电路（IC）的电路和技术。所公开的电路包括耦合到输出端子的单端输入 - 输出缓冲器。单端输入 - 输出缓冲器可用于将输入信号作为输出信号发送到输出端。用于锐化输出信号的第一边缘和第二边缘的预加重电路耦合在单端输入 - 输出缓冲器和输出端子之间。当输入信号从第一逻辑电平切换到第二逻辑电平时，输出信号的第一边缘被锐化，而当输入信号从第二逻辑电平切换到第一逻辑电平时，输出信号的第二边沿被锐化。

80. 发明授权

US06691267B1 Technique to test an integrated circuit using fewer pins 失效
标题翻译：使用较少引脚测试集成电路的技术
公开(公告)号：US06691267B1
公开(公告)日：2004-02-10
申请号：US09094221
申请日：1998-06-09
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Xiaobao Wang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Xiaobao Wang
IPC分类号： G01R3128
CPC分类号： H03K19/17764 , G01R31/318516 , G01R31/318555 , G06F11/2273 , H03K19/17744
摘要： A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a package with fewer pins. This technique may be used to implement test functions in a programmable logic device. Test data may be serially input using a test pin (310) for two or more columns (320) of logic blocks. The test data is stored in an A register (330), and may be later transferred into a B register (335).
摘要翻译：实现需要较少的集成电路引脚的功能以将数据串行传输到用于多个逻辑块的集成电路的技术。通过减少所需的引脚，可以将集成电路下降到具有较少引脚的封装中。该技术可用于在可编程逻辑器件中实现测试功能。测试数据可以使用针对逻辑块的两列或多列（320）的测试引脚（310）进行串行输入。测试数据存储在A寄存器（330）中，并且可以稍后传送到B寄存器（335）。

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