会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 75. 发明授权
      US06498522B2 Semiconductor device 有权
    • Semiconductor device
    • 半导体器件
    • US06498522B2
    • 2002-12-24
    • US09833045
    • 2001-04-12
    • Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
    • Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
    • H03L700
    • G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222
    • The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.
    • 本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。 根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号 接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 76. 发明授权
      US06452453B1 Constant-current generator, differential amplifier, and semiconductor integrated circuit 有权
    • Constant-current generator, differential amplifier, and semiconductor integrated circuit
    • 恒流发电机，差分放大器和半导体集成电路
    • US06452453B1
    • 2002-09-17
    • US09562289
    • 2000-05-01
    • Shinya Fujioka , Akihiro Funyu
    • Shinya Fujioka , Akihiro Funyu
    • H03F304
    • H03F1/301 , H03F2203/45456 , H03F2203/45508
    • The constant-current generator comprises a bias transistor whose drain and gate are connected to each other, and an outputting transistor. The threshold voltage of the outputting transistor is smaller than that of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. Therefore, the gate-to-source voltages of the outputting transistor and the bias transistor are always kept equal. On the other hand, the drain-to-source current of the outputting transistor becomes larger than that of the bias transistor in accordance with the difference between the threshold voltages of the outputting transistor and the bias transistor. Accordingly, the outputting transistor can output a stable drain-to-source current even when the drain voltage of the bias transistor has shifted to lower the gate-to-source voltage thereof.
    • 恒流发生器包括漏极和栅极彼此连接的偏置晶体管和输出晶体管。 输出晶体管的阈值电压小于偏置晶体管的阈值电压。 输出晶体管具有与偏置晶体管相同的源极电压和相同的栅极电压。 因此，输出晶体管和偏置晶体管的栅极 - 源极电压总是保持相等。 另一方面，根据输出晶体管和偏置晶体管的阈值电压之差，输出晶体管的漏极 - 源极电流变得大于偏置晶体管的漏极 - 源极电流。 因此，即使当偏置晶体管的漏极电压已经偏移以降低其栅极至源极电压时，输出晶体管也可以输出稳定的漏极 - 源极电流。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 78. 发明授权
      US06341100B1 Semiconductor integrated circuit having circuit for writing data to memory cell 有权
    • Semiconductor integrated circuit having circuit for writing data to memory cell
    • 具有用于将数据写入存储单元的电路的半导体集成电路
    • US06341100B1
    • 2002-01-22
    • US09575363
    • 2000-05-22
    • Shinya Fujioka
    • Shinya Fujioka
    • G11C800
    • G11C11/4076 , G11C7/1006 , G11C7/1072 , G11C11/4096 , G11C2207/229
    • A controlling signal generating unit generates a bit line controlling signal, a word line signal, a sense amplifier activating signal, and a column line signal. The bit line controlling signal activates a resetting circuit which resets a bit line. The word line signal controls the connection between a memory cell and the bit line which transmits data to the memory cell. The sense amplifier activating signal activates a sense amplifier which amplifies data transmitted to the bit line. The column line signal activates a column switch which transmits data to the bit line. The controlling signal generating unit activates predetermined signal(s) among the word line signal, the sense amplifier activating signal, the bit line controlling signal, and the column line signal at the start of a write operation. The controlling signal generating unit activates the remaining signal(s) after the acceptance of write data. Since the predetermined signal(s) is/are activated without the acceptance of write data, it is possible to make the activating timing of the remaining signal(s) earlier. This consequently reduces the time necessary for a write operation.
    • 控制信号产生单元产生位线控制信号，字线信号，读出放大器激活信号和列线信号。 位线控制信号激活复位位线的复位电路。 字线信号控制存储单元与向存储单元发送数据的位线之间的连接。 读出放大器激活信号激活读出放大器，其放大发送到位线的数据。 列线信号激活向位线发送数据的列开关。 控制信号产生单元在写入操作开始时激活字线信号，读出放大器激活信号，位线控制信号和列线信号之间的预定信号。 控制信号产生单元在接受写入数据之后激活剩余的信号。 由于在不接受写入数据的情况下激活预定信号，所以可以使剩余信号的激活定时更早。 这因此减少了写操作所需的时间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 79. 发明授权
      US06301173B2 Memory device with faster reset operation 有权
    • Memory device with faster reset operation
    • 具有更快复位操作的存储器件
    • US06301173B2
    • 2001-10-09
    • US09307758
    • 1999-05-10
    • Shinya Fujioka , Yasuharu Sato
    • Shinya Fujioka , Yasuharu Sato
    • G11C700
    • G11C7/065 , G11C7/12
    • The present invention is a memory circuit having a plurality of word lines, a plurality of bit line pairs, and memory cells disposed at the cross-position thereof. The memory comprises: a sense amplifier which is shared by the first bit line pair and the second bit line pair disposed in the column direction and amplifies a voltage of the bit line pairs; a first and a second bit line transfer gates which are disposed between the sense amplifier and the first and second bit line pairs, and connects the bit line pair at the selected memory cell side to the sense amplifier; a bit line clamper, which is disposed between the first and second bit line transfer gates, is shared by the first bit line pair and the second bit line pair, and supplies the precharge level to the bit line pairs; and a bit line short circuit, which is disposed at the first and the second bit line pairs respectively and shorts the bit line pairs. According to the above structure, the reset operation involving a bit line short operation can be executed at high-speed, since the bit line short circuit is disposed for each bit line pair. Also area efficiency can be improved since the bit line clamper circuit is shared by the first and the second bit line pairs.
    • 本发明是具有多个字线，多个位线对和设置在其交叉位置的存储单元的存储电路。 存储器包括：读出放大器，由第一位线对和位于列方向上的第二位线对共享，并放大位线对的电压; 第一位线传输门和第二位线传输门，其布置在读出放大器与第一和第二位线对之间，并将所选存储单元侧的位线对连接到读出放大器; 位于第一和第二位线传输门之间的位线钳位器由第一位线对和第二位线对共用，并将预充电电平提供给位线对; 以及分别布置在第一和第二位线对上并使位线对短路的位线短路。 根据上述结构，由于对每个位线对设置位线短路，所以可以高速执行涉及位线短路操作的复位动作。 由于位线钳位电路由第一位线对和第二位线对共享，所以可以提高面积效率。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号