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71. 发明申请

US20050023611A1 Field effect transistor having a doped gate electrode with reduced gate depletion and method of forming the transistor 有权
标题翻译：场效应晶体管具有栅极耗尽减少的掺杂栅极和形成晶体管的方法
公开(公告)号：US20050023611A1
公开(公告)日：2005-02-03
申请号：US10790852
申请日：2004-03-02
申请人： Karsten Wieczorek , Thomas Feudel , Thorsten Kammler , Wolfgang Buchholtz
发明人： Karsten Wieczorek , Thomas Feudel , Thorsten Kammler , Wolfgang Buchholtz
IPC分类号： H01L21/336 , H01L29/49 , H01L29/786 , H01L21/00 , H01L27/01
CPC分类号： H01L29/66553 , H01L29/4908 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66772 , H01L29/78618 , H01L29/78621 , H01L29/78636
摘要： By forming an implantation mask prior to the definition of the drain and the source areas, an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask, the lateral dimension of the gate electrode may be defined by well-established sidewall spacer techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.
摘要翻译：通过在漏极和源极区域的定义之前形成注入掩模，实现了栅极掺杂剂浓度与漏极和源极浓度的有效去耦。此外，在移除注入掩模之后，栅极的横向尺寸可以通过公认的侧壁间隔物技术来限定，从而相对于基于光刻和各向异性蚀刻的常规方法提供缩放优点。

72. 发明授权

US06821840B2 Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area 有权
标题翻译：包括场效应晶体管和无源电容器的半导体器件具有减小的漏电流和每单位面积的改善的电容
公开(公告)号：US06821840B2
公开(公告)日：2004-11-23
申请号：US10403481
申请日：2003-03-31
申请人： Karsten Wieczorek , Gert Burbach , Thomas Feudel
发明人： Karsten Wieczorek , Gert Burbach , Thomas Feudel
IPC分类号： H01L218242
CPC分类号： H01L27/0629 , H01L27/0805 , Y10S438/981
摘要： A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.
摘要翻译：半导体器件包括场效应晶体管和无源电容器，其中电容器的电介质层由高k材料构成，而场效应晶体管的栅极绝缘层由超薄氧化物层或氮氧化物层形成以便在栅极绝缘层和下面的沟道区域之间的界面处提供优异的载流子迁移率。由于电容器中的载流子迁移率不是很重要，所以高k材料允许提供每单位面积的高电容，同时具有足以有效减少泄漏电流的厚度。

73. 发明授权

US06812159B2 Method of forming a low leakage dielectric layer providing an increased capacitive coupling 有权
标题翻译：形成提供增加的电容耦合的低漏电介质层的方法
公开(公告)号：US06812159B2
公开(公告)日：2004-11-02
申请号：US10420635
申请日：2003-04-22
申请人： Karsten Wieczorek , Falk Graetsch , Lutz Herrmann
发明人： Karsten Wieczorek , Falk Graetsch , Lutz Herrmann
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31116 , H01L21/3115 , H01L29/518
摘要： A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.
摘要翻译：提供一种形成可用作将场电极与场效应晶体管的沟道区分离的介质的电介质层的方法，其允许高电容耦合同时仍然保持低的漏电流水平。这通过引入通过低能量等离子体照射来增加电介质层的电阻的掺杂剂例如氮来实现，其中选择初始层厚度以基本上避免掺杂剂渗透到下面的材料中。随后，通过原子层蚀刻去除电介质材料，以最终获得所需的设计厚度。

74. 发明授权

US06593197B2 Sidewall spacer based fet alignment technology 有权
公开(公告)号：US06593197B2
公开(公告)日：2003-07-15
申请号：US09811733
申请日：2001-03-19
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan , Michael Raab
IPC分类号： H01L21336
CPC分类号： H01L29/6659
摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

75. 发明授权

US06566718B2 Field effect transistor with an improved gate contact and method of fabricating the same 有权
公开(公告)号：US06566718B2
公开(公告)日：2003-05-20
申请号：US09848085
申请日：2001-05-03
申请人： Karsten Wieczorek , Rolf Stephan , Manfred Horstmann , Stephan Kruegel
发明人： Karsten Wieczorek , Rolf Stephan , Manfred Horstmann , Stephan Kruegel
IPC分类号： H01L2976
CPC分类号： H01L23/5222 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor comprises a gate electrode contact of a highly conductive material that contacts the gate electrode and extends in the transistor width dimension at least along a portion of the channel. Thus, the gate resistance and the gate signal propagation time for a voltage applied to the gate contact is significantly reduced even for devices with an extremely down scaled gate length. Moreover, a method for fabricating the above FET is disclosed.

76. 发明授权

US06491799B1 Method for forming a thin dielectric layer 失效
标题翻译：薄介电层的形成方法
公开(公告)号：US06491799B1
公开(公告)日：2002-12-10
申请号：US09766738
申请日：2001-01-22
申请人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
发明人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
IPC分类号： C23C1434
CPC分类号： C23C14/10 , C23C14/3407 , C23C14/3471
摘要： The method disclosed herein comprises initially providing a tool comprised of a process chamber, a lid above the process chamber, an RF coil for assisting in generating a plasma in the chamber, a substrate support, and a power supply coupled to the substrate support. The method continues with the step of positioning a substrate in the tool adjacent the substrate support, introducing a noble gas into the chamber, and forming a layer of material above the substrate by sputtering the lid material by performing at least the following steps: applying approximately 200-300 watts of power to the RF coil at a frequency of approximately 400 KHz and applying approximately 20-60 watts of power to the substrate at a frequency of approximately 13.56 MHz.
摘要翻译：本文公开的方法包括最初提供一种工具，其包括处理室，处理室上方的盖，用于辅助在室中产生等离子体的RF线圈，衬底支撑件和耦合到衬底支撑件的电源。该方法继续以下步骤：将衬底定位在邻近衬底支撑件的工具中，将惰性气体引入腔室中，以及通过至少执行以下步骤溅射盖材料在衬底上方形成材料层：近似施加以大约400KHz的频率向RF线圈施加200-300瓦的功率，并以大约13.56MHz的频率向衬底施加大约20-60瓦的功率。

77. 发明授权

US06268257B1 Method of forming a transistor having a low-resistance gate electrode 有权
标题翻译：形成具有低电阻栅电极的晶体管的方法
公开(公告)号：US06268257B1
公开(公告)日：2001-07-31
申请号：US09557714
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28247 , H01L29/6659
摘要： A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.
摘要翻译：公开了一种方法，其中晶体管的栅电极的低电阻部分形成为独立于在漏极和源极区域中形成低电阻部分。因此，该器件在栅电极中具有厚的低电阻部分，例如，通过最小化栅极电阻来支持低栅极延迟的厚栅极硅化物，以及漏极和源极中的薄的低电阻部分，以便满足浅结合整合的要求。此外，公开了一种具有低电阻栅极电极部分的晶体管，其组成不同于漏极和源极的低电阻部分。

78. 发明授权

US06218250B1 Method and apparatus for minimizing parasitic resistance of semiconductor devices 有权
标题翻译：用于最小化半导体器件的寄生电阻的方法和装置
公开(公告)号：US06218250B1
公开(公告)日：2001-04-17
申请号：US09324183
申请日：1999-06-02
申请人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
发明人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26586 , H01L21/28518 , H01L29/456 , H01L29/4933
摘要： A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.
摘要翻译：半导体器件包括衬底，栅极结构，多个侧壁间隔物和多个第一硅化物层。栅极结构位于衬底上方。多个侧壁间隔件邻近门结构定位。第一硅化物层位于衬底中并且具有在侧壁间隔物下方延伸的第一端。一种形成半导体器件的方法包括在衬底上形成栅极结构。在栅极结构附近形成多个侧壁间隔物。使用倾斜的注入工艺将注入材料设置到衬底中，所述倾斜注入工艺适于在衬底中形成第一注入区域。植入区域具有在侧壁间隔物下方延伸第一距离的第一端。

79. 发明授权

US6133124A Device improvement by source to drain resistance lowering through undersilicidation 有权
标题翻译：器件通过源极降低漏极电阻降低硅芯片
公开(公告)号：US6133124A
公开(公告)日：2000-10-17
申请号：US245951
申请日：1999-02-05
申请人： Manfred Horstmann , Karsten Wieczorek , Frederick N. Hause
发明人： Manfred Horstmann , Karsten Wieczorek , Frederick N. Hause
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/425 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.
摘要翻译：提供了制造硅化物层的各种方法，以及包含其的装置。一方面，提供了在基板上制造硅化物层的方法。该方法包括以下步骤：损坏位于间隔物下方的衬底的一部分的晶体结构并在衬底上沉积金属层。加热金属层和衬底以使金属与衬底反应并形成硅化物层，由此硅化物层的一部分横向延伸在衬垫下方。任何未反应的金属被去除。该方法能够制造具有大量横向侵入LDD结构的硅化物层，导致晶体管的可能的源极 - 漏极电阻和增强的性能。

80. 发明授权

US08188871B2 Drive current adjustment for transistors by local gate engineering 有权
标题翻译：通过局部门工程驱动晶体管的电流调节
公开(公告)号：US08188871B2
公开(公告)日：2012-05-29
申请号：US12472969
申请日：2009-05-27
申请人： Manfred Horstmann , Patrick Press , Karsten Wieczorek , Kerstin Ruttloff
发明人： Manfred Horstmann , Patrick Press , Karsten Wieczorek , Kerstin Ruttloff
IPC分类号： G08B17/00
CPC分类号： H01L21/823462 , H01L21/28035 , H01L21/823456 , H01L27/11 , H01L29/4238 , H01L29/513
摘要： In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.
摘要翻译：在存储器单元中，晶体管的驱动电流能力可以通过局部地提供存储单元的一个或多个晶体管的增加的栅介质厚度和/或栅极长度来调节。也就是说，栅极长度和/或栅极电介质厚度可以沿晶体管宽度方向变化，从而提供用于调节有效驱动电流能力的有效机构，同时允许使用有源区域的简化几何形状，这可能由于增加的工艺均匀性而导致产量提高。特别地，可能减少由硅化镍部分引起的产生短路的可能性。

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