专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US09000526B2 MOSFET structure with T-shaped epitaxial silicon channel 有权
标题翻译：具有T形外延硅通道的MOSFET结构
公开(公告)号：US09000526B2
公开(公告)日：2015-04-07
申请号：US13288189
申请日：2011-11-03
申请人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
发明人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762 , H01L29/66 , H01L29/10 , H01L21/265
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/76232 , H01L29/1033 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/167 , H01L29/66492 , H01L29/6659 , H01L29/66651 , H01L29/78 , H01L29/7833
摘要： A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
摘要翻译：设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。

72. 发明申请

US20140147069A1 BUFFER UNIT FOR SLEWING PLATFORM OF TAMPING MACHINE 有权
标题翻译：冲压机平台缓冲单元
公开(公告)号：US20140147069A1
公开(公告)日：2014-05-29
申请号：US13318282
申请日：2011-06-27
申请人： Jiwen Peng , Zhiqiang Wu , Weichan Qin , Wei Zhao
发明人： Jiwen Peng , Zhiqiang Wu , Weichan Qin , Wei Zhao
IPC分类号： E02D3/046 , E01C19/30 , E01C19/34 , E02D3/054
CPC分类号： E02D3/046 , E01C19/30 , E01C19/34 , E02D3/054 , F16C35/06 , F16C2300/14 , F16C2350/00
摘要： A buffer unit for the slewing platform of the tamping machine, comprising a slewing plafform, a slewing bearing and a chassis, the upper end of the said slewing bearing connects to the slewing plafform and the lower end of said slewing bearing connects to the chassis, the slewing platform can revolve around the chassis 360 degrees, further comprising a annular supporting slab, a hydraulic cylinder and a connecting rod, the annular supporting slab is fixed on the chassis by bolt. The hydraulic cylinder is fitted on the rear end of the central plane of the slewing platform, the piston rod head of the hydraulic cylinder connects to said connecting rod. The connecting rod can touch and support the annular base slab at any point of the direction of 360 degrees rotation when the hydraulic cylinder extends.
摘要翻译：一种用于捣固机的回转平台的缓冲单元，包括回转平台，回转支承和底盘，所述回转支承的上端连接到回转平板，而所述回转支承的下端连接到底盘，回转平台可围绕底盘360度旋转，还包括环形支撑板，液压缸和连杆，环形支撑板通过螺栓固定在底盘上。液压缸安装在回转平台的中心平面的后端，液压缸的活塞杆头连接到所述连杆。当液压缸延伸时，连杆可以在360度旋转方向的任何点处接触并支撑环形基板。

73. 发明授权

US08591847B2 Method for removing hydrogen sulfide from gaseous stream at normal temperature 有权
标题翻译：在常温下从气态物流中除去硫化氢的方法
公开(公告)号：US08591847B2
公开(公告)日：2013-11-26
申请号：US13172898
申请日：2011-06-30
申请人： Zhenyi Liu , Zhiqiang Wu , Xiangsheng Wang
发明人： Zhenyi Liu , Zhiqiang Wu , Xiangsheng Wang
IPC分类号： B01D53/52 , B01D53/80 , B01D53/96
CPC分类号： B01D53/52 , B01D2259/126
摘要： A wet desulfurizing method for removal of H2S from gaseous stream at normal temperature, the method including: (a) contacting and reacting the gaseous stream containing H2S with a suspension containing desulfurizer in a desulfurization reactor; (b) leading the suspension containing waste agent produced by desulfurizing of desulfurizer after the reaction in step (a) to a regenerative reactor, and regenerating the waste agent using an oxygen-containing gas; (c) leading the suspension containing desulfurizer regenerated in step (b) to the desulfurization reactor in step (a), and contacting and reacting with the gaseous stream containing H2S. A simple method for removing hydrogen sulfide from gas at room temperature and normal pressure, which features high desulfurization rate and low cost.
摘要翻译：一种在常温下从气态物流中除去H 2 S的湿式脱硫方法，该方法包括：（a）在脱硫反应器中使含有H 2 S的气态物流与含有脱硫剂的悬浮液接触和反应; （b）将在步骤（a）中反应后通过脱硫剂脱硫产生的废液引入再生反应器，并使用含氧气体再生废料; （c）将步骤（b）中再生的含有脱硫剂的悬浮液导入步骤（a）中的脱硫反应器，并与含有H 2 S的气态流接触并反应。在室温和常压下从气体中除去硫化氢的简单方法，脱硫率高，成本低。

74. 发明授权

US08487378B2 Non-uniform channel junction-less transistor 有权
标题翻译：不均匀沟道无结晶体管
公开(公告)号：US08487378B2
公开(公告)日：2013-07-16
申请号：US13077144
申请日：2011-03-31
申请人： Ken-Ichi Goto , Zhiqiang Wu
发明人： Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L27/12
CPC分类号： H01L29/66803 , G01N33/6893 , H01L29/785 , H01L2029/7857
摘要： The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.
摘要翻译：本公开公开了一种在衬底上形成半导体层的方法。该方法包括将半导体层图案化成翅片结构。该方法包括在鳍结构上形成栅介电层和栅电极层。该方法包括以栅极结构缠绕翅片结构的一部分的方式构图栅极电介质层和栅极电极层以形成栅极结构。该方法包括执行多个注入工艺以在散热片结构中形成源极/漏极区域。多个注入工艺以这样一种方式进行，使得跨鳍片结构的掺杂分布不均匀，鳍结构部分被栅极结构缠绕的部分的第一区域具有较低的掺杂浓度水平比其他地区的鳍结构。

75. 发明申请

US20130113041A1 SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE 有权
标题翻译：具有优化的DOPANT轮廓的半导体晶体管器件
公开(公告)号：US20130113041A1
公开(公告)日：2013-05-09
申请号：US13288201
申请日：2011-11-03
申请人： Chia-Wen LIU , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
发明人： Chia-Wen LIU , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66492 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/1045 , H01L29/105 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/7833 , Y10S438/931
摘要： Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
摘要翻译：提供了一种用于在半导体器件中形成晶体管的晶体管和方法。该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。使用具有非常低的倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。如此形成的晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。掺杂物分布还包括在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域的晶体管沟道。

76. 发明授权

US08435849B2 Method of forming a CMOS IC having a compressively stressed metal layer in the NMOS area 有权
标题翻译：在NMOS区域中形成具有压应力金属层的CMOS IC的方法
公开(公告)号：US08435849B2
公开(公告)日：2013-05-07
申请号：US13440344
申请日：2012-04-05
申请人： Xin Wang , Zhiqiang Wu , Ramesh Venugopal
发明人： Xin Wang , Zhiqiang Wu , Ramesh Venugopal
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , H01L29/7847
摘要： A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.
摘要翻译：公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成金属硅化物。用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

77. 发明申请

US20130056795A1 FinFET Design Controlling Channel Thickness 有权
公开(公告)号：US20130056795A1
公开(公告)日：2013-03-07
申请号：US13335689
申请日：2011-12-22
申请人： Zhiqiang Wu , Ken-Ichi Goto , Wen-Hsing Hsieh , Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang
发明人： Zhiqiang Wu , Ken-Ichi Goto , Wen-Hsing Hsieh , Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang
IPC分类号： H01L29/78 , H01L29/36 , H01L21/20 , H01L29/12
CPC分类号： H01L21/02362 , H01L21/02123 , H01L21/02293 , H01L21/0234 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.

78. 发明申请

US20090227084A1 Novel Method to Enhance Channel Stress in CMOS Processes 有权
标题翻译：在CMOS工艺中增强沟道应力的新方法
公开(公告)号：US20090227084A1
公开(公告)日：2009-09-10
申请号：US12357712
申请日：2009-01-22
申请人： Zhiqiang Wu , Xin Wang
发明人： Zhiqiang Wu , Xin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/7845 , H01L29/7847 , H01L29/7848
摘要： The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.
摘要翻译：本发明提供了一种制造半导体器件的方法，该半导体器件增强了传输到沟道区的载流子迁移率增强的应力量。在一个实施例中，在源极/漏极退火之前，在栅极电介质界面处或附近形成非晶区域。在第二实施例中，栅极材料是非晶态的，并且处理温度保持低于栅极材料结晶温度，直到应力增强处理完成。非晶栅极材料在高温退火期间变形，并从非晶态转变为多晶相，允许更多的应力传输到沟道区。这增强了载流子迁移率并改善了晶体管驱动电流。

79. 发明授权

US07189627B2 Method to improve SRAM performance and stability 有权
标题翻译：提高SRAM性能和稳定性的方法
公开(公告)号：US07189627B2
公开(公告)日：2007-03-13
申请号：US10921532
申请日：2004-08-19
申请人： Zhiqiang Wu , Shaofeng Yu , C. Rinn Cleavelin
发明人： Zhiqiang Wu , Shaofeng Yu , C. Rinn Cleavelin
IPC分类号： H01L21/76
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11
摘要： A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.
摘要翻译：公开了一种用于增加晶体管（300）的宽度的技术，同时可以缩小晶体管本身。通过在与晶体管（300）相邻的浅沟槽隔离（STI）区域（328）内形成凹槽（352）来增加晶体管宽度（382）。凹部（352）提供围绕晶体管的区域，从而增加晶体管（300）的宽度（382）。该环绕区域为掺杂剂原子沉积提供了额外的空间，这有助于随机掺杂剂波动（RDF）的减少。以这种方式，根据本发明的一个或多个方面形成的晶体管可以在并入SRAM时产生改善的性能，因为这种晶体管将更加紧密匹配的可能性增加。

80. 发明申请

US20060040462A1 Novel method to improve SRAM performance and stability 有权
标题翻译：提高SRAM性能和稳定性的新方法
公开(公告)号：US20060040462A1
公开(公告)日：2006-02-23
申请号：US10921532
申请日：2004-08-19
申请人： Zhiqiang Wu , Shaofeng Yu , C. Cleavelin
发明人： Zhiqiang Wu , Shaofeng Yu , C. Cleavelin
IPC分类号： H01L21/76
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11
摘要： A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.
摘要翻译：公开了一种用于增加晶体管（300）的宽度的技术，同时可以缩小晶体管本身。通过在与晶体管（300）相邻的浅沟槽隔离（STI）区域（328）内形成凹槽（352）来增加晶体管宽度（382）。凹部（352）提供围绕晶体管的区域，从而增加晶体管（300）的宽度（382）。该环绕区域为掺杂剂原子沉积提供了额外的空间，这有助于随机掺杂剂波动（RDF）的减少。以这种方式，根据本发明的一个或多个方面形成的晶体管可以在并入SRAM时产生改善的性能，因为这种晶体管将更加紧密匹配的可能性增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式