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71. 发明申请

US20050133830A1 Method for fabricating a recessed channel filed effect transistor (FET) device 失效
标题翻译：凹陷通道场效应晶体管（FET）器件的制造方法
公开(公告)号：US20050133830A1
公开(公告)日：2005-06-23
申请号：US10739476
申请日：2003-12-17
申请人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
发明人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L29/786 , H01L21/8234 , H01L29/76 , H01L31/113
CPC分类号： H01L29/66772 , H01L29/66545 , H01L29/66621 , H01L29/78621 , H01L29/78654
摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
摘要翻译：用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。根据上述特征，以增强的性能制造场效应晶体管器件。

72. 发明申请

US20050118755A1 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US20050118755A1
公开(公告)日：2005-06-02
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L29/40
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

73. 发明申请

US20050106888A1 Method of in-situ damage removal - post O2 dry process 审中-公开
标题翻译：原位损伤去除方法 - 后O2干法
公开(公告)号：US20050106888A1
公开(公告)日：2005-05-19
申请号：US10714207
申请日：2003-11-14
申请人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
IPC分类号： G03F7/42 , H01L21/302 , H01L21/306 , H01L21/311 , H01L21/461 , H01L21/768
CPC分类号： H01L21/31116 , G03F7/427 , H01L21/02046 , H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814
摘要： An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.
摘要翻译：公开了一种集成工艺流程，其包括用于除去光致抗蚀剂层的氧灰化之后的氧化物残余物的等离子体步骤。氧化物去除步骤在防止微掩模缺陷方面是有效的，并且优选在用于氧灰化步骤的相同处理室和用于图案转移的后续等离子体蚀刻中进行。氧化物去除步骤需要少于60秒，并且涉及从NF 3，Cl 2，CF 4，...中的一个或多个产生的含卤素等离子体， SUB 2，CH 2，2 F 2和SF 6。可选地，HBr或碳氟化合物其中x和y是整数，z是整数或等于0可以是可以单独使用或与上述含卤素气体中的一种一起使用。氧化物去除步骤可以结合在各种应用中，包括镶嵌方案，浅沟槽（STI）制造或在晶体管中形成栅电极。

74. 发明授权

US06867084B1 Gate structure and method of forming the gate dielectric with mini-spacer 有权
标题翻译：用微型间隔物形成栅极电介质的栅结构和方法
公开(公告)号：US06867084B1
公开(公告)日：2005-03-15
申请号：US10263541
申请日：2002-10-03
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

75. 发明授权

US06864193B2 Aqueous cleaning composition containing copper-specific corrosion inhibitor 失效
标题翻译：含有铜特异性缓蚀剂的水性清洗组合物
公开(公告)号：US06864193B2
公开(公告)日：2005-03-08
申请号：US10379769
申请日：2003-03-05
申请人： Chun-Li Chou , Hun-Jan Tao , Peng-Fu Hsu
发明人： Chun-Li Chou , Hun-Jan Tao , Peng-Fu Hsu
IPC分类号： C11D7/26 , C11D7/50 , C11D11/00 , H01L21/00 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/321 , H01L21/461
CPC分类号： H01L21/02063 , C11D7/261 , C11D7/263 , C11D7/265 , C11D7/267 , C11D7/5022 , C11D11/0047 , Y10S438/905 , Y10S438/906
摘要： A composition and method for fabricating a semiconductor wafer containing copper is disclosed, which method includes plasma etching a dielectric layer from the surface of the wafer, plasma ashing a resist from the surface of the wafer, and cleaning the wafer surface by contacting same with a cleaning formulation, which includes the following components and their percentage by weight ranges shown: (a) from about 0.01 to 80% by weight organic solvent, (b) from about 0.01 to 30% by weight copper chelating agent, (c) from about 0.01 to 10% by weight copper inhibitor, and (d) from about 0.01 to 70% by weight water.
摘要翻译：公开了一种用于制造含有铜的半导体晶片的组合物和方法，该方法包括从晶片的表面等离子体蚀刻介电层，等离子体从晶片的表面灰化抗蚀剂，以及通过使晶片表面与清洁制剂，其包括以下组分及其重量百分比范围：（a）约0.01至80重量％的有机溶剂，（b）约0.01至30重量％的铜螯合剂，（c）约 0.01〜10重量％的铜抑制剂，（d）约0.01〜70重量％的水。

76. 发明授权

US06828248B1 Method of pull back for forming shallow trench isolation 失效
标题翻译：用于形成浅沟槽隔离的拉回方法
公开(公告)号：US06828248B1
公开(公告)日：2004-12-07
申请号：US10637350
申请日：2003-08-08
申请人： Hun-Jan Tao , Huan-Just Lin
发明人： Hun-Jan Tao , Huan-Just Lin
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L21/76232
摘要： A method of pull back for a shallow trench isolation (STI) structure is provided. The method firstly provides a substrate having a hard mask layer disposed thereupon and a dielectric layer above the hard mask layer. Then a trench is formed within the hard mask layer, the dielectric layer and the substrate. Finally, the hard mask layer and the dielectric layer are pulled back by using a halogen containing etching process.
摘要翻译：提供了一种用于浅沟槽隔离（STI）结构的拉回方法。该方法首先提供具有设置在其上的硬掩模层和硬掩模层上方的电介质层的衬底。然后在硬掩模层，电介质层和衬底内形成沟槽。最后，通过使用含卤素蚀刻工艺将硬掩模层和电介质层拉回。

77. 发明授权

US06821880B1 Process of dual or single damascene utilizing separate etching and DCM apparati 失效
标题翻译：使用单独蚀刻和DCM装置的双或单镶嵌工艺
公开(公告)号：US06821880B1
公开(公告)日：2004-11-23
申请号：US10725138
申请日：2003-12-01
申请人： Hun-Jan Tao , Chao-Cheng Chen
发明人： Hun-Jan Tao , Chao-Cheng Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76814 , H01L21/67155 , H01L21/76801 , H01L21/76808 , H01L21/76838
摘要： A process of dual damascene or damascene. The dual damascene process entails providing an etching apparatus, a DCM machine and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, a contact, and a photoresist layer. The dielectric layer and the contact are etched in the etching apparatus to form a trench. The photoresist and the contact are ashed in the DCM machine. Finally the wafer is wet cleaned.
摘要翻译：一个双镶嵌或镶嵌的过程。双镶嵌工艺需要提供蚀刻装置，DCM机器和晶片，晶片具有金属线，阻挡层，介电层，接触和光致抗蚀剂层。在蚀刻装置中蚀刻介电层和接触以形成沟槽。在DCM机器中将光致抗蚀剂和接触物灰化。最后将晶片湿式清洗。

78. 发明授权

US06764903B1 Dual hard mask layer patterning method 失效
标题翻译：双硬掩模层图案化方法
公开(公告)号：US06764903B1
公开(公告)日：2004-07-20
申请号：US10427451
申请日：2003-04-30
申请人： Bor-Wen Chan , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Bor-Wen Chan , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21336
CPC分类号： H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.
摘要翻译：从覆盖目标层形成图案化目标层的方法采用层叠在覆盖目标层上的一对覆盖层硬掩模层。在其上形成图案化的第三掩模层。该方法还采用四个独立的蚀刻步骤。一个蚀刻步骤是用于从橡皮布上面的硬掩模层形成图案化的上卧硬掩模层的各向异性蚀刻步骤。然后在第二蚀刻步骤中各向同性蚀刻图案化的上卧硬掩模层，以形成各向同性蚀刻的图案化的上面的硬掩模层。该方法对于形成半导体产品中线宽减小和尺寸控制增强的栅电极特别有用。

79. 发明授权

US06498067B1 Integrated approach for controlling top dielectric loss during spacer etching 有权
标题翻译：在间隔蚀刻期间控制顶部介电损耗的集成方法
公开(公告)号：US06498067B1
公开(公告)日：2002-12-24
申请号：US10139021
申请日：2002-05-02
申请人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
发明人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L29/6656
摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.
摘要翻译：已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物间隔

80. 发明授权

US06472335B1 Methods of adhesion promoter between low-K layer and underlying insulating layer 有权
标题翻译：低K层和下层绝缘层之间的粘附促进剂的方法
公开(公告)号：US06472335B1
公开(公告)日：2002-10-29
申请号：US09175019
申请日：1998-10-19
申请人： Chia-Shiung Tsai , Yao-Yi Cheng , Hun-Jan Tao
发明人： Chia-Shiung Tsai , Yao-Yi Cheng , Hun-Jan Tao
IPC分类号： H01L2131
CPC分类号： H01L21/0214 , H01L21/02118 , H01L21/022 , H01L21/02343 , H01L21/31111 , H01L21/312 , H01L21/3122 , H01L21/3124 , H01L21/3144 , H01L21/31629 , H01L21/3185 , H01L21/76801 , Y10S438/906 , Y10S438/958 , Y10S438/964
摘要： The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.
摘要翻译：本发明提供一种通过在形成上覆低K层之前进行HF浸渍蚀刻来处理氧化物，氮化硅或氮氧化硅绝缘层的表面来改善金属间电介质（IMD）层之间的粘合力的方法。本发明提供了一种在氧化物，氮氧化硅（SiON）或氮化物IMD层14上制备低K IMD层20的方法，其具有改善的粘合性。首先，在衬底上形成第一金属间介电层（IMD）层14。接下来，在第一IMD层14上进行本发明的新型HF浸渍蚀刻以形成处理表面16.接下来，在第一IMD层14的粗糙表面16上形成由低K材料构成的第二BMD层。经处理的表面16改善了第一IMD层氧化物（氧化物，SiN或SiON）和低k层之间的粘合性。随后的光刻胶条步骤不会导致第一IMI层14和第二IMD层20（低K电介质）剥离。

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