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71. 发明授权

US07547942B2 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07547942B2
公开(公告)日：2009-06-16
申请号：US11709816
申请日：2007-02-23
申请人： Sang-Hun Jeon , Chang-Seok Kang , Jung-Dal Choi , Jin-Taek Park , Woong-Hee Sohn , Won-Seok Jung
发明人： Sang-Hun Jeon , Chang-Seok Kang , Jung-Dal Choi , Jin-Taek Park , Woong-Hee Sohn , Won-Seok Jung
IPC分类号： H01L21/00
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L29/518 , H01L29/78
摘要： A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.
摘要翻译：非易失性存储器件包括：包括单元区域和外围电路区域的半导体衬底，单元区域上的单元栅极和外围电路区域上的外围电路栅极，其中，所述单元栅极包括半导体上的电荷存储绝缘层基板，电荷存储绝缘层上的栅极电极和栅电极上的导电层，外围电路栅极包括在半导体基板上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层和欧姆层上的导电层。

72. 发明授权

US07195966B2 Methods of fabricating semiconductor devices including polysilicon resistors and related devices 有权
标题翻译：制造包括多晶硅电阻器和相关器件的半导体器件的方法
公开(公告)号：US07195966B2
公开(公告)日：2007-03-27
申请号：US11011644
申请日：2004-12-14
申请人： Jin-Taek Park , Jung-Dal Choi , Jung-Young Lee , Hyun-Suk Kim
发明人： Jin-Taek Park , Jung-Dal Choi , Jung-Young Lee , Hyun-Suk Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/0629 , H01L27/11521 , H01L27/11524 , Y10S438/97
摘要： Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a portion of an upper surface of the first interlayer insulating layer is exposed. A resistor pattern is provided in the trench such that the at least a portion of the resistor pattern contacts the exposed portion of the first interlayer insulating layer. Related methods are also provided.
摘要翻译：提供制造半导体器件的方法。晶体管设置在半导体衬底上。第一层间绝缘层设置在晶体管上。在第一层间绝缘层上设置第二层间绝缘层。第二层间绝缘层限定使第一层间绝缘层的上表面的至少一部分露出的沟槽。电阻图案设置在沟槽中，使得电阻图案的至少一部分接触第一层间绝缘层的暴露部分。还提供了相关方法。

73. 发明申请

US20070259505A1 NON-VOLATILE MEMORY DEVICES AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20070259505A1
公开(公告)日：2007-11-08
申请号：US11613329
申请日：2006-12-20
申请人： Young-Woo Park , Jung-Dal Choi
发明人： Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L21/02
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11568
摘要： Non-volatile memory devices and methods for forming the same are provided. A device isolation layer may be formed on the semiconductor substrate to define an active region. A tunneling insulation pattern, a charge storage pattern, and a blocking insulation pattern may be disposed on the active region. A gate electrode may be disposed on the blocking insulation pattern. The charge storage pattern may be arranged in a matrix and a lower surface thereof is higher than an upper surface of the device isolation layer.
摘要翻译：提供非易失性存储器件及其形成方法。可以在半导体衬底上形成器件隔离层以限定有源区。隧道绝缘图案，电荷存储图案和阻挡绝缘图案可以设置在有源区域上。栅电极可以设置在阻挡绝缘图案上。电荷存储图案可以布置成矩阵并且其下表面高于器件隔离层的上表面。

74. 发明申请

US20110117722A1 Semiconductor Device With Charge Storage Pattern And Method For Fabricating The Same 有权
标题翻译：具有电荷存储模式的半导体器件及其制造方法
公开(公告)号：US20110117722A1
公开(公告)日：2011-05-19
申请号：US13011607
申请日：2011-01-21
申请人： Young-Woo Park , Jung-Dal Choi , Jae-Sung Sim
发明人： Young-Woo Park , Jung-Dal Choi , Jae-Sung Sim
IPC分类号： H01L21/28
CPC分类号： H01L27/11568
摘要： A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns.
摘要翻译：具有改进的数据保留特性的半导体器件（例如，非易失性存储器件）包括突出在器件隔离区的顶表面上方的有源区。在有源区上形成隧道绝缘层。电荷存储模式（例如，电荷陷阱图案）被形成为彼此间隔开。在电荷存储图案上形成阻挡绝缘层和栅极。

75. 发明授权

US07893484B2 Semiconductor device with charge storage pattern and method for fabricating the same 有权
标题翻译：具有电荷存储模式的半导体器件及其制造方法
公开(公告)号：US07893484B2
公开(公告)日：2011-02-22
申请号：US11683383
申请日：2007-03-07
申请人： Young-Woo Park , Jung-Dal Choi , Jae-Sung Sim
发明人： Young-Woo Park , Jung-Dal Choi , Jae-Sung Sim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568
摘要： A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns.
摘要翻译：具有改进的数据保留特性的半导体器件（例如，非易失性存储器件）包括突出在器件隔离区的顶表面上方的有源区。在有源区上形成隧道绝缘层。电荷存储模式（例如，电荷陷阱图案）被形成为彼此间隔开。在电荷存储图案上形成阻挡绝缘层和栅极。

76. 发明授权

US08546870B2 Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices 有权
标题翻译：具有具有不同宽度的导电图案的栅极结构的半导体器件和制造这种器件的方法
公开(公告)号：US08546870B2
公开(公告)日：2013-10-01
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

77. 发明授权

US08232170B2 Methods for fabricating semiconductor devices with charge storage patterns 有权
标题翻译：用于制造具有电荷存储模式的半导体器件的方法
公开(公告)号：US08232170B2
公开(公告)日：2012-07-31
申请号：US13011607
申请日：2011-01-21
申请人： Young-Woo Park , Jung-Dal Choi , Jae-Sung Sim
发明人： Young-Woo Park , Jung-Dal Choi , Jae-Sung Sim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568
摘要： Provided are methods for fabricating semiconductor devices. A method may include forming a device isolation layer to define active regions on a semiconductor substrate. The active regions may protrude above an upper surface of the device isolation layer. The method may also include forming tunnel insulating layers on upper and side surfaces of corresponding ones of the active regions. The method may further include forming charge storage patterns on corresponding ones of the tunnel insulating layers. The charge storage patterns may be separated from each other. The method may also include forming a blocking insulating layer on the charge storage patterns and the device isolation layer. The method may further include forming a gate electrode on the blocking insulating layer. The blocking insulating layer may cover the device isolation layer such that the gate electrode is precluded from contact with the device isolation layer and the tunnel insulating layers.
摘要翻译：提供制造半导体器件的方法。一种方法可以包括形成器件隔离层以限定半导体衬底上的有源区。有源区可以突出在器件隔离层的上表面上方。该方法还可以包括在对应的活性区域的上表面和侧表面上形成隧道绝缘层。该方法还可以包括在相应的隧道绝缘层上形成电荷存储模式。电荷存储图案可以彼此分离。该方法还可以包括在电荷存储图案和器件隔离层上形成阻挡绝缘层。该方法还可以包括在阻挡绝缘层上形成栅电极。阻挡绝缘层可以覆盖器件隔离层，使得栅电极不被阻止与器件隔离层和隧道绝缘层接触。

78. 发明申请

US20100133604A1 Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices 有权
标题翻译：具有具有不同宽度的导电图案的门结构的半导体器件和制造这种器件的方法
公开(公告)号：US20100133604A1
公开(公告)日：2010-06-03
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

79. 发明申请

US20150214478A1 VARIABLE RESISTANCE MEMORY DEVICES 有权
标题翻译：可变电阻存储器件
公开(公告)号：US20150214478A1
公开(公告)日：2015-07-30
申请号：US14457439
申请日：2014-08-12
申请人： Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
发明人： Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1233 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/08 , H01L45/1675
摘要： A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.
摘要翻译：可变电阻存储器件包括多个第一导线，多个第二导线，多个存储单元，多个第一气隙和多个第二气隙。第一导线沿第一方向延伸。第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。存储单元包括可变电阻器件。存储单元位于第一导线和第二导线的交叉区域。第一气隙在存储单元之间沿第一方向延伸。第二气隙沿第二方向在存储单元之间延伸。

80. 发明授权

US08629489B2 Nonvolatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08629489B2
公开(公告)日：2014-01-14
申请号：US13357350
申请日：2012-01-24
申请人： Chang-Hyun Lee , Jung-Dal Choi
发明人： Chang-Hyun Lee , Jung-Dal Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/1052 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.
摘要翻译：非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

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