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71. 发明授权

US08614121B2 Method of manufacturing back gate triggered silicon controlled rectifiers 有权
标题翻译：制造背栅触发硅控整流器的方法
公开(公告)号：US08614121B2
公开(公告)日：2013-12-24
申请号：US13306488
申请日：2011-11-29
申请人： Robert J. Gauthier, Jr. , Junjun Li
发明人： Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L21/00
CPC分类号： H01L27/0262 , H01L29/7436
摘要： Back gate triggered silicon controlled rectifiers (SCR) and methods of manufacture are disclosed. The method includes forming a first diffusion type and a second diffusion type in a semiconductor layer of a silicon on insulator (SOI) substrate. The method further includes forming a back gate of a first diffusion type in a substrate under an insulator layer of the SOI substrate. The method further includes forming raised diffusion regions of a first dopant type and a second dopant type, adjacent to the second diffusion type and the first diffusion type, respectively. The back gate is formed to cover the second diffusion type, the first diffusion type and the second dopant type of the raised diffusion regions.
摘要翻译：背栅触发硅控整流器（SCR）及其制造方法。该方法包括在绝缘体上硅（SOI）衬底的半导体层中形成第一扩散型和第二扩散型。该方法还包括在SOI衬底的绝缘体层之下的衬底中形成第一扩散型的背栅。该方法还包括分别形成与第二扩散型和第一扩散型相邻的第一掺杂剂类型和第二掺杂剂类型的凸起扩散区域。后栅极形成为覆盖第二扩散型，第一扩散型和第二掺杂型的凸起扩散区。

72. 发明申请

US20130256749A1 PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES 有权
标题翻译： FINFET集成电路技术的被动设备
公开(公告)号：US20130256749A1
公开(公告)日：2013-10-03
申请号：US13431456
申请日：2012-03-27
申请人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
发明人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H01L29/739 , G06F17/50 , H01L21/331
CPC分类号： H01L21/845 , H01L27/0262 , H01L27/1211
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。形成器件结构，其包括器件区域中的第一导电类型的阱和阱中的第二导电性的掺杂区域。器件区域由绝缘体上半导体衬底的器件层的一部分组成。掺杂区域和阱的第一部分限定了结。阱的第二部分位于器件区域的掺杂区域和外部侧壁之间。可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

73. 发明授权

US08390068B2 Electrostatic discharge protection device and method of fabricating same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US08390068B2
公开(公告)日：2013-03-05
申请号：US13361051
申请日：2012-01-30
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L27/01 , H01L29/74 , H01L23/62
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

74. 发明申请

US20120146150A1 SELF-PROTECTED ELECTROSTATIC DISCHARGE FIELD EFFECT TRANSISTOR (SPESDFET), AN INTEGRATED CIRCUIT INCORPORATING THE SPESDFET AS AN INPUT/OUTPUT (I/O) PAD DRIVER AND ASSOCIATED METHODS OF FORMING THE SPESDFET AND THE INTEGRATED CIRCUIT 有权
标题翻译：自保护静电放电场效应晶体管（SPESDFET），集成电路作为输入/输出（I / O）PAD驱动器的SPESDFET和相关的形成SPESDFET和集成电路的方法
公开(公告)号：US20120146150A1
公开(公告)日：2012-06-14
申请号：US12967114
申请日：2010-12-14
申请人： Robert J. Gauthier, JR. , Mahender Kumar , Junjun Li , Dustin K. Slisher
发明人： Robert J. Gauthier, JR. , Mahender Kumar , Junjun Li , Dustin K. Slisher
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L23/60 , H01L27/0266 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.
摘要翻译：公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。另外，栅极结构可以是硅化的或非硅化的。利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

75. 发明授权

US08039868B2 Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure 有权
标题翻译：静电放电（ESD）可控硅整流（SCR）结构的结构和方法
公开(公告)号：US08039868B2
公开(公告)日：2011-10-18
申请号：US12342228
申请日：2008-12-23
申请人： Robert J. Gauthier, Jr. , Junjun Li , Aniket Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Aniket Srivastava
IPC分类号： H01L29/72 , H01L29/74
CPC分类号： H01L29/66386 , H01L24/06 , H01L27/0262 , H01L29/74 , H01L29/7436 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括形成在衬底中的第一和第二可控硅整流器（SCR）。此外，第一和第二SCR各自包括在第一和第二SCR之间共同共享的至少一个部件。

76. 发明申请

US20090206367A1 Design Structure and Method for a Silicon Controlled Rectifier (SCR) Structure for SOI Technology 有权
标题翻译：用于SOI技术的硅控整流器（SCR）结构的设计结构和方法
公开(公告)号：US20090206367A1
公开(公告)日：2009-08-20
申请号：US12031084
申请日：2008-02-14
申请人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/7436 , H01L27/0259 , H01L29/861
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

77. 发明授权

US07518845B2 RC-triggered power clamp suppressing negative mode electrostatic discharge stress 失效
标题翻译： RC触发功率钳位抑制负模式静电放电应力
公开(公告)号：US07518845B2
公开(公告)日：2009-04-14
申请号：US11422608
申请日：2006-06-07
申请人： Robert J. Gauthier, Jr. , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Robert J. Gauthier, Jr. , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.
摘要翻译：一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。另外，提供了电路中ESD保护的方法。该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

78. 发明申请

US20090086391A1 Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit 失效
标题翻译：具有BigFET门上拉电路的堆叠电源钳位
公开(公告)号：US20090086391A1
公开(公告)日：2009-04-02
申请号：US11865820
申请日：2007-10-02
申请人： Robert J. Gauthier, JR. , Junjun Li
发明人： Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
摘要翻译：一种用于保护集成电路芯片免受ESD事件的电子放电（ESD）保护电路。 ESD保护电路包括一叠BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及响应于ESD事件触发BigFET栅极驱动器来驱动BigFET的栅极。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

79. 发明申请

US20080308837A1 VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE SUCH AS A SILICON CONTROLLED RECTIFIER AND METHOD OF FORMING VERTICAL SOI CURRENT CONTROLLED DEVICES 有权
标题翻译：绝缘体（SOI）器件上的垂直电流控制硅如硅控制整流器及形成垂直SOI电流控制器件的方法
公开(公告)号：US20080308837A1
公开(公告)日：2008-12-18
申请号：US11762811
申请日：2007-06-14
申请人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher S. Putnam
发明人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher S. Putnam
IPC分类号： H01L29/74 , H01L21/20 , H01L21/332 , H01L21/84 , H01L29/00
CPC分类号： H01L27/0262
摘要： A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.
摘要翻译：具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。器件通过SOI表面层和绝缘体层形成在晶种孔中。通过衬底中的种子孔形成例如N型的掩埋扩散。掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。可以在掺杂的外延层上形成多晶硅，例如P型。与埋入扩散部的接触形成在接触衬里中。

80. 发明授权

US08987073B2 Self-protected metal-oxide-semiconductor field-effect transistor 有权
标题翻译：自保护金属氧化物半导体场效应晶体管
公开(公告)号：US08987073B2
公开(公告)日：2015-03-24
申请号：US13546509
申请日：2012-07-11
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L21/00 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/66
CPC分类号： H01L23/60 , H01L21/84 , H01L27/0251 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
摘要翻译：金属氧化物半导体场效应晶体管的器件结构，设计结构和制造方法。栅极结构形成在衬底的顶表面上。第一和第二沟槽形成在与栅极结构的侧壁相邻的衬底中。第二沟槽横向形成在第一沟槽和第一侧壁之间。第一和第二外延层分别形成在第一和第二沟槽中。形成到作为漏极的第一外延层的接触。第二沟槽中的第二外延层不接触，使得第二外延层用作镇流电阻器。

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