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    • 76. 发明授权
    • Receiver codec super set constellation generator
    • 接收机编解码器超集星座发生器
    • US07339996B2
    • 2008-03-04
    • US10804914
    • 2004-03-19
    • Sigang QiuVedavalli Gomatam KrishnanBo Zhang
    • Sigang QiuVedavalli Gomatam KrishnanBo Zhang
    • H04B14/04H04L5/16
    • H04L5/1453H04L25/4927
    • A technique is proposed to accurately estimate the Network CODEC levels for each PCM code a server modem generates. These levels are affected by the digital impairments such as Digital attenuation PAD in the trunk, the Robbed Bit Signaling, the type of CODEC (μ-law or a-law—or non standard), and by analog impairments such as loop distortion, noise, inter-modulation distortion, echo. At client modem equalizer output good estimates for these levels are derived. By detecting RBS pattern of the trunk, and using averages of decode levels of similar RBS slots, more accurate data points are obtained. By further replacing these levels with the closest CODEC receive levels, good accuracy is obtained. Non-monotonic points are detected and eliminated. An upper limit is set for constellation points to avoid saturation of the receiver. IMD correction is applied to the decode levels. Ideal points that are not signaled, are added if possible. When PAD-detection or Codec detection fails, PAD is set to 0 dB and the constellation is based on originally received and averaged data points. Techniques are presented for V.90 type modem constellation generation.
    • 提出了一种技术来准确地估计服务器调制解调器生成的每个PCM码的网络CODEC电平。 这些电平受到数字损伤的影响,例如中继线中的数字衰减PAD,Robbed位信令,CODEC的类型(mu律或a律或非法),以及模拟损伤,如环路失真,噪声 ,互调失真,回波。 在客户端调制解调器均衡器输出这些级别的良好估计值得出。 通过检测中继线的RBS模式,并使用类似RBS时隙的解码电平的平均值,可获得更准确的数据点。 通过以最接近的CODEC接收电平进一步取代这些电平,获得良好的精度。 检测和消除非单调点。 设置星座点的上限以避免接收器饱和。 解码级别应用IMD校正。 没有发出信号的理想点,如果可能的话添加。 当PAD检测或编解码检测失败时,PAD设置为0 dB,星座基于原始接收和平均数据点。 提出了V.90型调制解调器星座生成技术。
    • 77. 发明授权
    • Loop back testing structure for high-speed serial bit stream TX and RX chip set
    • 环回测试结构,用于高速串行比特流TX和RX芯片组
    • US07313097B2
    • 2007-12-25
    • US10390490
    • 2003-03-17
    • Ali GhiasiBo Zhang
    • Ali GhiasiBo Zhang
    • H04L1/00H04L12/26
    • H04L1/243
    • A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a loop back circuitry. A bit stream demultiplexer includes an input ordering block, a plurality of demultiplexers, and an output ordering block. During testing, the transmit multiplexing integrated circuit and the receive demultiplexing integrated circuit are coupled into a circuit tester. Then, a plurality of input lines of the transmit multiplexing integrated circuit are coupled to a plurality of output data lines of the circuit tester. A loop back output of the transmit multiplexing integrated circuit is then coupled to a loop back input of the receive demultiplexing integrated circuit. A plurality of output lines of the receive demultiplexing integrated circuit are coupled to a plurality of input data lines of the circuit tester. Further, loop back control signals of the transmit multiplexing integrated circuit and the receive demultiplexing integrated circuit are coupled to control outputs of the circuit tester. The circuit tester is then operated to test the functionality of the integrated circuits.
    • 比特流多路复用器包括输入排序块,多个多路复用器,输出排序块和环回电路。 比特流解复用器包括输入排序块,多个解复用器和输出排序块。 在测试期间,发射多路复用集成电路和接收解复用集成电路耦合到电路测试器中。 然后,发送多路复用集成电路的多条输入线耦合到电路测试器的多条输出数据线。 然后,发射多路复用集成电路的环回输出耦合到接收解复用集成电路的环回输入。 接收解复用集成电路的多条输出线耦合到电路测试器的多条输入数据线。 此外,发送多路复用集成电路和接收解复用集成电路的环回控制信号被耦合到电路测试器的控制输出。 然后操作电路测试器来测试集成电路的功能。
    • 79. 发明授权
    • Synchronous data serialization circuit
    • 同步数据串行化电路
    • US07298301B2
    • 2007-11-20
    • US10919093
    • 2004-08-16
    • Bo Zhang
    • Bo Zhang
    • H03M9/00
    • H03M9/00H03K3/356043H03K3/356139H03K3/3562H03K17/04106H03K17/693H03K2005/00208H04J3/047
    • In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.
    • 根据本发明,数据处理电路包括用于处理第一数据的第一数据路径。 第一数据路径包括第一数据存储电路。 提供第二数据路径用于处理第二数据。 第二数据路径包括第二数据存储电路。 具有耦合到第一数据路径的第一输入和耦合到第二数据路径的第二输入的多路复用器接收存储的值。 复用器包括耦合到时钟信号的选择输入。 延迟电路被配置为延迟第二数据存储电路中的第二数据的存储,其中第一数据存储电路响应于接收到第一定时信号而存储第一数据,并且第二数据存储电路存储第二数据作为响应 以接收第二定时信号。