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71. 发明授权

US06541385B2 Method for plasma etching of Ir-Ta-O electrode and for post-etch cleaning 失效
公开(公告)号：US06541385B2
公开(公告)日：2003-04-01
申请号：US09855393
申请日：2001-05-14
申请人： Hong Ying , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
发明人： Hong Ying , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , C04B41/009 , C04B41/5346 , C04B41/91 , C04B2111/00844 , H01L21/32136 , H01L28/60 , C04B35/495
摘要： A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.

72. 发明授权

US06441417B1 Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same 失效
标题翻译：用于非易失性存储器应用的ZrO 2上的单个c轴PGO薄膜及其制造方法
公开(公告)号：US06441417B1
公开(公告)日：2002-08-27
申请号：US09820022
申请日：2001-03-28
申请人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
发明人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
IPC分类号： H01L2972
CPC分类号： H01L21/28291 , H01L21/31604 , H01L21/31691 , H01L28/56 , H01L29/516
摘要： A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.
摘要翻译：薄膜结构包括用于金属铁电绝缘体半导体单晶体管非易失性存储器应用的绝缘体上的基本单相c轴PGO膜。 PGO绝缘体结构也可用于电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件中。在优选实施例中，PGO膜沉积在氧化锆绝缘体层上。

73. 发明授权

US6071782A Partial silicidation method to form shallow source/drain junctions 失效
标题翻译：部分硅化法形成浅源极/漏极结
公开(公告)号：US6071782A
公开(公告)日：2000-06-06
申请号：US23383
申请日：1998-02-13
申请人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
发明人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/78 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L21/28052 , H01L29/6659
摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.
摘要翻译：提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。首先，低温退火开始跨越源/漏电极表面的盐析过程。控制时间和温度，使得金属仅被部分消耗。中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。然后，在较高温度的退火下完成硅化。由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

74. 发明授权

US5989965A Nitride overhang structures for the silicidation of transistor electrodes with shallow junction 失效
标题翻译：氮化硅突出结构用于具有浅结的晶体管电极的硅化
公开(公告)号：US5989965A
公开(公告)日：1999-11-23
申请号：US23032
申请日：1998-02-13
申请人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
发明人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6656
摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.
摘要翻译：提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。还提供了通过上述方法制造的具有突出结构的晶体管。

75. 发明申请

US20070290288A1 Floating body germanium phototransistor having a photo absorption threshold bias region 有权
标题翻译：具有光吸收阈值偏置区域的浮体锗光电晶体管
公开(公告)号：US20070290288A1
公开(公告)日：2007-12-20
申请号：US11894938
申请日：2007-08-22
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/10
CPC分类号： H01L31/1136
摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.
摘要翻译：提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。在一个方面，第二S / D区域具有比第一S / D长度更长的长度。光吸收阈值偏置区域位于第二S / D区域的下方。或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

76. 发明申请

US20060281232A1 Method of growing a germanium epitaxial film on insulator for use in fabrication of a CMOS integrated circuit 有权
标题翻译：在绝缘体上生长用于制造CMOS集成电路的锗外延膜的方法
公开(公告)号：US20060281232A1
公开(公告)日：2006-12-14
申请号：US11149891
申请日：2005-06-10
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L21/84
CPC分类号： H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L29/78684
摘要： A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer; patterning and etching the polycrystalline germanium; encapsulating the polycrystalline germanium with an insulating material; rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium; cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium, thereby forming a single crystal germanium layer; and completing the CMOS device.
摘要翻译：制造硅 - 锗CMOS的方法包括制备硅衬底晶片; 在硅衬底晶片上沉积绝缘层; 图案化和蚀刻绝缘层; 在所述绝缘层和所述硅衬底晶片的至少一部分上沉积多晶锗层; 图案化和蚀刻多晶锗; 用绝缘材料封装多晶锗; 在足以熔化多晶锗的温度下快速热退火晶片; 冷却晶片以促进多晶锗的液相外延，从而形成单晶锗层; 并完成CMOS设备。

77. 发明申请

US20060194415A1 Germanium infrared sensor for CMOS imagers 有权
标题翻译：锗红外传感器用于CMOS成像器
公开(公告)号：US20060194415A1
公开(公告)日：2006-08-31
申请号：US11069422
申请日：2005-02-28
申请人： Jong-Jan Lee , Jer-Shen Maa , Sheng Hsu , Douglas Tweet
发明人： Jong-Jan Lee , Jer-Shen Maa , Sheng Hsu , Douglas Tweet
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/14634 , H01L27/14649 , H01L27/14689 , H01L27/1469 , H01L31/028 , H01L31/103 , H01L31/1804 , H01L31/1808 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on a silicon substrate; depositing a layer of refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.
摘要翻译：制造用于CMOS成像器的锗红外传感器的方法包括制备施主晶片，其包括：离子注入到硅晶片中以形成P +硅层; 在P +硅层上生长外延锗层，形成硅 - 锗界面; 循环退火; 以及将氢离子注入至少与P +硅层一样深的深度以形成缺陷层; 制备处理晶片，包括：在硅衬底上制造CMOS集成电路; 沉积难熔金属层; 处理供体晶片的表面和用于结合的处理晶片; 结合处理晶片和施主晶片以形成结合结构; 沿着缺陷层分离粘结结构; 在锗层上沉积一层氧化铟锡; 完成IR传感器。

78. 发明申请

US20050070115A1 Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction 失效
标题翻译：通过层压转移在绝缘体上制备松弛硅锗的方法
公开(公告)号：US20050070115A1
公开(公告)日：2005-03-31
申请号：US10677005
申请日：2003-09-30
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas Tweet , Sheng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas Tweet , Sheng Hsu
IPC分类号： H01L21/20 , H01L21/302 , H01L21/461 , H01L21/762
CPC分类号： H01L21/76254
摘要： A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 Å to 1 μm below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括在硅衬底上沉积硅 - 锗层以形成硅/硅 - 锗部分; 在硅 - 锗/硅界面之下的约500埃至1微米处将氢离子注入到硅衬底中; 将硅/硅锗部分接合到绝缘体基板上以形成对联体; 在第一热退火步骤中对联接件进行热退火以分离联接件; 图案化和蚀刻绝缘体上硅部分以去除部分硅和SiGe层; 蚀刻绝缘体上硅部分以除去剩余的硅层; 在第二退火步骤中对绝缘体上硅部分进行热退火以松弛SiGe层; 以及在SiGe层周围沉积一层应变硅。

79. 发明申请

US20070170536A1 Liquid phase epitaxial GOI photodiode with buried high resistivity germanium layer 审中-公开
标题翻译：液相外延GOI光电二极管，埋置高电阻率锗层
公开(公告)号：US20070170536A1
公开(公告)日：2007-07-26
申请号：US11339011
申请日：2006-01-25
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/00
CPC分类号： H01L31/1055 , H01L31/1808 , H01L31/1872 , Y02E10/50
摘要： A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N diode is formed with an n +-doped (n+) mesa, a p+-doped (p+) Ge bottom insulator interface and mesa lateral interface, and a high resistivity Ge layer interposed between the p+ Ge and n+ Ge. A metal electrode is formed overlying a region of the p+ Ge lateral interface, and a transparent electrode is formed overlying the n+ Ge mesa. In one aspect, the method deposits a silicon nitride layer temporary cap overlying the high resistivity Ge layer, and an annealing is performed to epitaxially crystallize the Ge bottom interface and high resistivity Ge layer.
摘要翻译：提供了一种用于制造具有埋置的高电阻率锗（Ge）层的液相外延（LPE）绝缘体锗绝缘体（GOI）光电二极管的器件和相关方法。该方法提供硅（Si）衬底，并且形成具有Si种子存取区域的覆盖Si衬底的底部绝缘体。然后，形成具有n +掺杂（n +）台面，p +掺杂（p +）Ge底部绝缘体界面和台面侧面界面的Ge P-I-N二极管，以及插入在p + Ge和n + Ge之间的高电阻率Ge层。在p + Ge侧面界面的区域上形成金属电极，形成覆盖n + Ge台面的透明电极。在一个方面，该方法沉积覆盖高电阻率Ge层的氮化硅层临时盖，并进行退火以使Ge底界面和高电阻率Ge层外延结晶。

80. 发明申请

US20070141744A1 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US20070141744A1
公开(公告)日：2007-06-21
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
发明人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the born-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在天然掺杂锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火激活N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

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