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71. 发明申请

US20060097299A1 Semiconductor device including capacitor and method of fabricating same 失效
标题翻译：包括电容器的半导体器件及其制造方法
公开(公告)号：US20060097299A1
公开(公告)日：2006-05-11
申请号：US11258619
申请日：2005-10-24
申请人： Jae-Young Ahn , Jin-Tae Noh , Hee-Seok Kim , Jin-Gyun Kim , Ju-Wan Lim , Sang-Ryol Yang , Hong-Suk Kim , Sung-Hae Lee
发明人： Jae-Young Ahn , Jin-Tae Noh , Hee-Seok Kim , Jin-Gyun Kim , Ju-Wan Lim , Sang-Ryol Yang , Hong-Suk Kim , Sung-Hae Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L27/10814 , H01L27/10882 , H01L27/10894 , H01L28/60 , H01L28/91
摘要： A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.
摘要翻译：半导体器件包括具有底部电极的电容器，形成在底部电极上的电介质层，形成在电介质层上的顶部电极和具有与顶部电极连接的金属的接触插塞，其中顶部电极包括掺杂的多晶硅1-x Ge层和外延沉积在掺杂的多晶Si-x Ge层上的掺杂多晶硅层并且接触插塞与掺杂多晶硅层接触。

72. 发明授权

US06962876B2 Method for forming a low-k dielectric layer for a semiconductor device 有权
公开(公告)号：US06962876B2
公开(公告)日：2005-11-08
申请号：US10981731
申请日：2004-11-05
申请人： Jae-Young Ahn , Jin-Gyun Kim , Hee-Seok Kim , Jin-Tae No , Sang-Ryol Yang , Sung-Hae Lee , Hong-Suk Kim , Ju-Wan Lim , Young-Seok Kim , Yong-Woo Hyung , Man-Sug Kang
发明人： Jae-Young Ahn , Jin-Gyun Kim , Hee-Seok Kim , Jin-Tae No , Sang-Ryol Yang , Sung-Hae Lee , Hong-Suk Kim , Ju-Wan Lim , Young-Seok Kim , Yong-Woo Hyung , Man-Sug Kang
IPC分类号： C23C16/30 , C23C16/44 , C23C16/455 , H01L21/318 , H01L21/321 , H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , C23C16/30 , C23C16/45531 , H01L21/02274 , H01L21/318 , H01L21/3185 , H01L21/3211
摘要： A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

73. 发明申请

US20050229087A1 Decoding apparatus for low-density parity-check codes using sequential decoding, and method thereof 失效
标题翻译：用于使用顺序解码的低密度奇偶校验码的解码装置及其方法
公开(公告)号：US20050229087A1
公开(公告)日：2005-10-13
申请号：US11105922
申请日：2005-04-13
申请人： Sunghwan Kim , Yong-June Kim , Jong-Seon No , Sang-Hyun Lee , Yun-Hee Kim , Jae-Young Ahn
发明人： Sunghwan Kim , Yong-June Kim , Jong-Seon No , Sang-Hyun Lee , Yun-Hee Kim , Jae-Young Ahn
IPC分类号： G06F11/00 , H03M13/00 , H03M13/11
CPC分类号： H03M13/6356 , H03M13/1105 , H03M13/114 , H03M13/6362
摘要： Disclosed is a decoding apparatus for LDPC (Low-Density Parity-Check) codes when receiving data encoded with LDPC codes on a channel having consecutive output values, and a method thereof. The decoding method for LDPC codes uses sequential decoding and includes: (a) dividing nodes into check nodes for a parity-check message and variable nodes for a bit message according to a parity-check matrix; (b) dividing the check nodes into a predetermined number of subsets; (c) sequentially decoding the LDPC codeword of each subset for all the check nodes; (d) generating an output message for verifying validity of the decoding result; and (e) iteratively performing the steps (b), (c), and (d) by a predetermined number of iterations.
摘要翻译：公开了一种在具有连续输出值的信道上接收用LDPC码编码的数据时的LDPC（低密度奇偶校验）码的解码装置及其方法。 LDPC码的解码方法使用顺序解码，并且包括：（a）根据奇偶校验矩阵将节点划分成用于奇偶校验消息的校验节点和用于位消息的可变节点; （b）将校验节点划分成预定数量的子集; （c）对于所有校验节点顺序解码每个子集的LDPC码字; （d）生成用于验证解码结果的有效性的输出消息; 和（e）以预定次数的迭代迭代地执行步骤（b），（c）和（d）。

74. 发明授权

US06815350B2 Method for forming a thin film using an atomic layer deposition (ALD) process 有权
标题翻译：使用原子层沉积（ALD）工艺形成薄膜的方法
公开(公告)号：US06815350B2
公开(公告)日：2004-11-09
申请号：US10378681
申请日：2003-03-05
申请人： Young-Seok Kim , Yong-Woo Hyung , Man-Sung Kang , Jae-Young Ahn
发明人： Young-Seok Kim , Yong-Woo Hyung , Man-Sung Kang , Jae-Young Ahn
IPC分类号： H01L2131
CPC分类号： H01L21/0228 , C23C16/30 , C23C16/45531 , H01L21/02112 , H01L21/02274 , H01L21/318 , H01L21/3185 , H01L21/3211
摘要： A method for forming a ternary thin film using an atomic layer deposition process includes supplying a first and a second reactive material to a chamber containing a wafer, the first and second reactive materials being adsorbing on a surface of the wafer, supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, supplying a third reactive material to the chamber to cause a reaction between the first and second reactive materials and the third reactive material to form a thin film monolayer, supplying a second gas to purge the third reactive material that remains unreacted and a byproduct, and repeating the above steps for forming the thin film monolayer a predetermined number of times to form a ternary thin film having a predetermined thickness on the wafer. Preferably, the ternary thin film is a SiBN film.

75. 发明授权

US09530899B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09530899B2
公开(公告)日：2016-12-27
申请号：US14474942
申请日：2014-09-02
申请人： Bi O Kim , Jin-Tae Noh , Su-Jin Shin , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi O Kim , Jin-Tae Noh , Su-Jin Shin , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/792 , H01L27/115 , G11C16/04 , H01L21/28 , H01L29/66
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11582 , H01L29/66833
摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括交替层叠在基板上的绝缘层和栅极电极，垂直通过绝缘层和栅电极的垂直沟道，以及设置在垂直线之间的阈值电压控制绝缘层，隧道绝缘层和电荷存储层沟道和栅电极，其中所述阈值电压控制绝缘层设置在所述电荷存储层和所述垂直沟道之间，并且包括被配置为抑制在所述垂直沟道中形成反型层的材料。

76. 发明授权

US09368646B2 Memory devices and methods of manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US09368646B2
公开(公告)日：2016-06-14
申请号：US14182325
申请日：2014-02-18
申请人： Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/792 , H01L29/66
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/66833
摘要： A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.
摘要翻译：垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上顺序地形成在每个沟道的侧壁上。所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

77. 发明授权

US09129857B2 Semiconductor device including a first core pattern under a second core pattern 有权
标题翻译：半导体器件包括在第二芯图案下的第一芯图案
公开(公告)号：US09129857B2
公开(公告)日：2015-09-08
申请号：US13560022
申请日：2012-07-27
申请人： Bi-O Kim , Byong-Ju Kim , Jung-Geun Jee , Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Byong-Ju Kim , Jung-Geun Jee , Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/792 , H01L27/115 , H01L21/336
CPC分类号： H01L27/1157 , H01L27/11582 , H01L29/105
摘要： According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.
摘要翻译：根据示例性实施例，半导体器件包括堆叠在衬底上的水平图案。水平图案通过水平图案定义开口。第一个核心模式是在开幕。第一个核心模式是第一个核心模式的开放。第一活动模式在第一芯图案和水平图案之间。包含第一元件的第二活动图案位于第二芯图案和水平图案之间。第二活性图案含有比第二芯图案中的第一元素的浓度高的浓度的第一元素。

78. 发明申请

US20150145021A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20150145021A1
公开(公告)日：2015-05-28
申请号：US14517025
申请日：2014-10-17
申请人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
发明人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
IPC分类号： H01L27/115 , H01L29/51
CPC分类号： H01L27/11565 , H01L27/1158 , H01L29/66833 , H01L29/7926
摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.
摘要翻译：非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

79. 发明申请

US20150129954A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20150129954A1
公开(公告)日：2015-05-14
申请号：US14474942
申请日：2014-09-02
申请人： Bi O. Kim , Jin-Tae Noh , Su-Jin Shin , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi O. Kim , Jin-Tae Noh , Su-Jin Shin , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11582 , H01L29/66833
摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括交替层叠在基板上的绝缘层和栅极电极，垂直通过绝缘层和栅电极的垂直沟道，以及设置在垂直线之间的阈值电压控制绝缘层，隧道绝缘层和电荷存储层沟道和栅电极，其中所述阈值电压控制绝缘层设置在所述电荷存储层和所述垂直沟道之间，并且包括被配置为抑制在所述垂直沟道中形成反型层的材料。

80. 发明申请

US20140024189A1 Vertical Memory Devices and Methods of Manufacturing the Same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140024189A1
公开(公告)日：2014-01-23
申请号：US13943911
申请日：2013-07-17
申请人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/8239 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.
摘要翻译：提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

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