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71. 发明申请

US20060091908A1 Level shift circuit for use in semiconductor device 有权
标题翻译：用于半导体器件的电平移位电路
公开(公告)号：US20060091908A1
公开(公告)日：2006-05-04
申请号：US11030615
申请日：2005-01-05
申请人： Hee-Bok Kang , Jin-Hong Ahn
发明人： Hee-Bok Kang , Jin-Hong Ahn
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356147
摘要： A level shifter for use in a semiconductor device, includes: a first transferring unit for transferring an input signal to an inverted output node in response to a negative voltage; a second transferring unit for supplying a power supply voltage to an output node in response to the input signal; and a third transferring unit coupled to the inverted output node and the output node for supplying the negative voltage to the output node in response to an output of the first transferring unit.
摘要翻译：一种用于半导体器件的电平转换器，包括：第一传送单元，用于响应于负电压将输入信号传送到反相输出节点; 第二传送单元，用于响应于所述输入信号向输出节点提供电源电压; 以及耦合到所述反相输出节点和所述输出节点的第三传送单元，用于响应于所述第一传送单元的输出将所述负电压提供给所述输出节点。

72. 发明申请

US20060091902A1 Data input buffer in semiconductor device 失效
标题翻译：半导体器件中的数据输入缓冲器
公开(公告)号：US20060091902A1
公开(公告)日：2006-05-04
申请号：US11027631
申请日：2004-12-29
申请人： Hee-Bok Kang , Jin-Hong Ahn
发明人： Hee-Bok Kang , Jin-Hong Ahn
IPC分类号： H03K19/003
CPC分类号： H03K19/018528
摘要： A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second input terminal respectively in order to detect a voltage level of the input data signal based on a result of comparing the input data signal with the reference voltage in response to a clock enable signal inputted through a third input terminal; and a noise elimination unit connected between the first input terminal and the third input terminal for eliminating a noise of the reference voltage signal.
摘要翻译：一种用于半导体器件的数据输入缓冲器，包括：检测单元，用于分别通过第一输入端和第二输入端接收参考电压信号和输入数据信号，以便检测输入数据信号的电压电平基于通过第三输入端子输入的时钟使能信号，比较输入数据信号与参考电压的结果; 以及噪声消除单元，连接在第一输入端和第三输入端之间，用于消除参考电压信号的噪声。

73. 发明申请

US20060091900A1 Semiconductor memory device with on die termination circuit 失效
标题翻译：半导体存储器件，带芯片终端电路
公开(公告)号：US20060091900A1
公开(公告)日：2006-05-04
申请号：US11030558
申请日：2005-01-05
申请人： Hee-Bok Kang , Jin-Hong Ahn
发明人： Hee-Bok Kang , Jin-Hong Ahn
IPC分类号： H03K19/003
CPC分类号： H04L25/0284
摘要： A semiconductor memory device having a data input/output pad connected to a data input node includes: an on die termination resistor one end of which is connected to the data input node; and a switch one end of which is connected to the other end of the on die termination resistor for connecting/disconnecting the on die termination resistor with an on die termination voltage.
摘要翻译：具有连接到数据输入节点的数据输入/输出焊盘的半导体存储器件包括：一端连接到数据输入节点的芯片上终端电阻; 并且其一端的开关连接到管芯终端电阻器的另一端，用于连接/断开带有芯片端接电压的管芯终端电阻器。

74. 发明授权

US6005826A Address signal transition detecting circuit for semiconductor memory device 失效
标题翻译：用于半导体存储器件的地址信号转换检测电路
公开(公告)号：US6005826A
公开(公告)日：1999-12-21
申请号：US54469
申请日：1998-04-03
申请人： Jin-Hong Ahn , Oh-Sang Yoon
发明人： Jin-Hong Ahn , Oh-Sang Yoon
IPC分类号： G11C11/41 , G11C8/18 , G11C11/407 , G11C11/409 , G11C29/00 , G11C7/00
CPC分类号： G11C8/18
摘要： An address signal transition detecting apparatus includes an address transition detecting circuit for detecting transitions in address signals, accordingly generating address transition detection signals and summing the address transition detection signals to generate an address transition detection sum signal ATDSUM, respectively outputting a first pulse signal YE for activating a column address decoder, a second pulse signal P for activating a precharger and a third pulse signal SE for activating a sense amplifier in accordance with an address transition detecting sum signal ATDSUM, and once again outputting another first pulse signal YE for activating the column address decoder in response to a fourth pulse signal YE2 generated in accordance with the address transition detection sum signal ATDSUM and the first pulse signal YE. The apparatus enables accurately reading a data signal on a data line by twice generating the first pulse signal YE that serves to activate the column address decoder, whereby the sense amplifier is able to sense a data signal in an improved manner.
摘要翻译：地址信号转换检测装置包括地址转换检测电路，用于检测地址信号中的转变，从而产生地址转换检测信号，并且对地址转变检测信号求和以产生地址转换检测和信号ATDSUM，分别输出第一脉冲信号YE，激活列地址解码器，用于激活预充电器的第二脉冲信号P和用于根据地址转换检测和信号ATDSUM激活读出放大器的第三脉冲信号SE，并再次输出用于激活列的另一第一脉冲信号YE 响应于根据地址转换检测和信号ATDSUM生成的第四脉冲信号YE2和第一脉冲信号YE，地址解码器。该装置能够通过两次产生用于激活列地址解码器的第一脉冲信号YE来精确地读取数据线上的数据信号，由此读出放大器能够以改进的方式感测数据信号。

75. 发明授权

US08000164B2 Self refresh operation of semiconductor memory device 有权
公开(公告)号：US08000164B2
公开(公告)日：2011-08-16
申请号：US12724394
申请日：2010-03-15
申请人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
发明人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/20 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C2211/4061
摘要： A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

76. 发明授权

US07957212B2 Pseudo SRAM 失效
标题翻译：伪SRAM
公开(公告)号：US07957212B2
公开(公告)日：2011-06-07
申请号：US11395897
申请日：2006-03-30
申请人： Hee-Bok Kang , Jin-Hong Ahn
发明人： Hee-Bok Kang , Jin-Hong Ahn
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406
摘要： A unit memory cell for use in a pseudo static random access memory (SRAM) includes a cell capacitor; a normal accessing transistor whose gate, drain and source are respectively connected to a normal accessing word line, a normal accessing bit line and a storage node of the cell capacitor; and a refresh accessing transistor whose gate, drain and source are respectively connected to a refresh accessing word line, a refresh accessing bit line and the storage node of the cell capacitor.
摘要翻译：用于伪静态随机存取存储器（SRAM）的单元存储单元包括单元电容器; 正常访问晶体管的栅极，漏极和源极分别连接到单元电容器的正常访问字线，正常访问位线和存储节点; 以及刷新存取晶体管，其栅极，漏极和源极分别连接到刷新访问字线，刷新存取位线和单元电容器的存储节点。

77. 发明授权

US07710809B2 Self refresh operation of semiconductor memory device 有权
标题翻译：半导体存储器件的自刷新操作
公开(公告)号：US07710809B2
公开(公告)日：2010-05-04
申请号：US11786594
申请日：2007-04-12
申请人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
发明人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/20 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C2211/4061
摘要： A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.
摘要翻译：一种用于驱动半导体存储器件的方法，包括初始化与单元阵列中包括的每个对应行的刷新时间对应的第一数据; 在进入自刷新模式之后存储对应于包括在第一行中的列数据的第二数据; 根据对于预定的刷新周期的基于对应的第一数据选择的刷新周期，在对单元阵列中的其他行执行刷新操作的同时，通过检测第一行的刷新时间来设置与第一行对应的第一数据，其中刷新在预定的刷新周期期间不对第一行执行操作; 将第二数据恢复到第一行; 并对其他行重复上述步骤，从而设置对应的第一数据，直到完成所有行的设置步骤或自刷新模式期满。

78. 发明授权

US07417910B2 Low voltage semiconductor memory device 失效
标题翻译：低电压半导体存储器件
公开(公告)号：US07417910B2
公开(公告)日：2008-08-26
申请号：US11133420
申请日：2005-05-18
申请人： Hee-Bok Kang , Jin-Hong Ahn
发明人： Hee-Bok Kang , Jin-Hong Ahn
IPC分类号： G11C7/00 , G11C5/14 , G11C7/02
CPC分类号： G11C11/4076 , G11C11/4091 , G11C2207/2227
摘要： A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference metal oxide semiconductor (MOS) transistor for connecting the reference capacitor to the bit line, and a second reference MOS transistor for connecting the reference capacitor to the bit line bar; and a third reference MOS transistor coupled to the reference cell block for charging the reference capacitor with a reference voltage.
摘要翻译：一种具有用于读取或存储数据的单元阵列区域的半导体存储器件，包括：包括多个正常单元的正常单元块，每个正常单元均耦合到位线和位线条之一，用于存储数据; 包括多个参考单元单元的参考单元块，每个参考单元单元包括参考电容器，用于将参考电容器连接到位线的第一参考金属氧化物半导体（MOS）晶体管和用于将参考电容器连接到位线条以及耦合到参考电池块的第三参考MOS晶体管，用于用参考电压对参考电容器充电。

79. 发明授权

US07359268B2 Semiconductor memory device for low voltage 失效
标题翻译：用于低电压的半导体存储器件
公开(公告)号：US07359268B2
公开(公告)日：2008-04-15
申请号：US11319080
申请日：2005-12-28
申请人： Hee-Bok Kang , Jin-Hong Ahn
发明人： Hee-Bok Kang , Jin-Hong Ahn
IPC分类号： G11C7/00
CPC分类号： G11C11/4097 , G11C11/4096 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/output (I/O) switching unit for transferring the read data from a segment data line pair to the local data line pair and for transferring the write data from the local data line pair to the segment data line pair, wherein each of the local data line pair and the segment line pair includes a VDD precharge block.
摘要翻译：半导体存储器件包括用于将数据从本地数据线对传送到全局数据线的读取放大单元作为读取数据; 用于将写数据从全局数据线传送到本地数据线对的写驱动器; 以及用于将读取的数据从段数据线对传送到本地数据线对并将写入数据从本地数据线对传送到段数据线对的输入/输出（I / O）切换单元，其中每个的本地数据线对和分段线对包括VDD预充电块。

80. 发明授权

US07358797B2 Semiconductor device having secure operating characteristic under low power environment 有权
标题翻译：半导体器件在低功率环境下具有安全的工作特性
公开(公告)号：US07358797B2
公开(公告)日：2008-04-15
申请号：US11320833
申请日：2005-12-30
申请人： Hee-Bok Kang , Jin-Hong Ahn
发明人： Hee-Bok Kang , Jin-Hong Ahn
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G11C2207/2227
摘要： Provided is a semiconductor device that can secure a current consumption characteristic and an operating speed characteristic under a low power voltage environment. The semiconductor device is divided into a plurality of regions depending on the current consumption characteristics. Considering the current consumption characteristics of the corresponding regions, the ground voltage or the negative voltage is supplied as the base voltage. For example, in the memory region or the logic region, which exhibits the single transient low current characteristic, the negative voltage is supplied as the base voltage. On the contrary, in the output driver circuit region, the DLL or the PLL, which exhibits the high current characteristics, the ground voltage is supplied as the base voltage. In this case, the operating speed characteristic can be secured even under the low power supply environment without decreasing the threshold voltage of the transistor. In addition, the current consumption can be minimized in the power-down mode or the standby mode.
摘要翻译：提供一种能够在低功率电压环境下确保电流消耗特性和工作速度特性的半导体装置。根据电流消耗特性，半导体器件被分成多个区域。考虑到相应区域的电流消耗特性，提供接地电压或负电压作为基极电压。例如，在存在单一瞬态低电流特性的存储区域或逻辑区域中，作为基极电压供给负电压。相反，在输出驱动器电路区域中，具有高电流特性的DLL或PLL提供接地电压作为基极电压。在这种情况下，即使在低电源环境下也能够确保工作转速特性，而不降低晶体管的阈值电压。此外，在掉电模式或待机模式下，电流消耗可以最小化。

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