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71. 发明授权

US5937289A Providing dual work function doping 失效
标题翻译：提供双重功能掺杂
公开(公告)号：US5937289A
公开(公告)日：1999-08-10
申请号：US3106
申请日：1998-01-06
申请人： Gary Bela Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William Robert Tonti
发明人： Gary Bela Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William Robert Tonti
IPC分类号： H01L21/225 , H01L21/28 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L21/8238
CPC分类号： H01L21/28035 , H01L21/82345
摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.
摘要翻译：通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选定数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。还提供了栅极结构的阵列，其中各个栅极结构在其顶部部分上包含自对准的绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。

72. 发明授权

US07253066B2 MOSFET with decoupled halo before extension 失效
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US07253066B2
公开(公告)日：2007-08-07
申请号：US10785895
申请日：2004-02-24
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/6659
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

73. 发明授权

US07129557B2 Autonomic thermal monitor and controller for thin film devices 失效
标题翻译：用于薄膜器件的自动热监测器和控制器
公开(公告)号：US07129557B2
公开(公告)日：2006-10-31
申请号：US10853800
申请日：2004-05-25
申请人： Zachary E. Berndlmaier , Edward W. Kiewra , Carl J. Radens , William R. Tonti
发明人： Zachary E. Berndlmaier , Edward W. Kiewra , Carl J. Radens , William R. Tonti
IPC分类号： H01L31/058
CPC分类号： H01L27/0248 , G01K7/01 , H01L29/66992
摘要： A thermal monitor diode is provided that comprises a silicon thin film on an insulator mounted on a silicon substrate. An opening extends through the silicon thin film and through the insulator and partially into the silicon substrate and terminates at an end wall. A conductive material is disposed in the opening and extends to the end wall. The substrate has a P/N junction formed therein adjacent the end wall, and an insulating spacer material surrounds the conductive material and is sufficiently thin to allow temperature excursions in the silicon thin film to pass therethrough. The invention also contemplates a method of forming the diode.
摘要翻译：提供一种热监测二极管，其包括安装在硅衬底上的绝缘体上的硅薄膜。开口延伸穿过硅薄膜并穿过绝缘体并部分地延伸到硅衬底中并终止于端壁。导电材料设置在开口中并延伸到端壁。衬底具有邻近端壁形成的P / N结，并且绝缘间隔物材料围绕导电材料并且足够薄以允许硅薄膜中的温度偏移通过。本发明还考虑了形成二极管的方法。

74. 发明授权

US07078259B2 Method for integrating thermistor 失效
标题翻译：热敏电阻集成方法
公开(公告)号：US07078259B2
公开(公告)日：2006-07-18
申请号：US10707746
申请日：2004-01-08
申请人： Jon A. Casey , William J. Ferrante , Edward W. Kiewra , Carl J. Radens , William R. Tonti
发明人： Jon A. Casey , William J. Ferrante , Edward W. Kiewra , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/00
CPC分类号： H01L21/76895 , G01K7/226 , H01C7/006 , H01L21/76224 , H01L21/76838
摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).
摘要翻译：提供了用于形成热敏电阻的结构和方法。隔离结构形成在至少包括单晶半导体的上层的基板中。一层自杀化合物前体沉积在隔离区和上层上。然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

75. 发明授权

US07674675B2 Method of forming an integrated SOI fingered decoupling capacitor 失效
标题翻译：形成集成的SOI手指去耦电容器的方法
公开(公告)号：US07674675B2
公开(公告)日：2010-03-09
申请号：US11485599
申请日：2006-07-12
申请人： Zachary E. Berndlmaier , Edward W. Kiewra , Carl J. Radens , William R. Tonti
发明人： Zachary E. Berndlmaier , Edward W. Kiewra , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1087 , H01L27/1203
摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.
摘要翻译：本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物，具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

76. 发明授权

US06730552B1 MOSFET with decoupled halo before extension 有权
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US06730552B1
公开(公告)日：2004-05-04
申请号：US10604096
申请日：2003-06-26
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

77. 发明授权

US07064410B2 MOS antifuse with low post-program resistance 有权
公开(公告)号：US07064410B2
公开(公告)日：2006-06-20
申请号：US10872173
申请日：2004-06-18
申请人： Carl J. Radens , William R. Tonti
发明人： Carl J. Radens , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an increased intersection perimeter between edge regions of a first conductor and portions of a second conductor is disclosed. In one embodiment, the intersection perimeter is the region where the perimeter of a gate structure overlaps an active area. The intersection perimeter between the conductors directs the breakdown of the dielectric material, increasing the likelihood that the programming event will be successful. In at least one embodiment, the portion of a current path that travels through a highly doped area is increased while the portion that travels through a non-highly doped area is decreased. This decreases post-program resistance, leading to better response time for the device.

78. 发明授权

US06794726B2 MOS antifuse with low post-program resistance 有权
标题翻译： MOS反熔丝，后编程电阻低
公开(公告)号：US06794726B2
公开(公告)日：2004-09-21
申请号：US10063376
申请日：2002-04-17
申请人： Carl J. Radens , William R. Tonti
发明人： Carl J. Radens , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an increased intersection perimeter between edge regions of a first conductor and portions of a second conductor is disclosed. In one embodiment, the intersection perimeter is the region where the perimeter of a gate structure overlaps an active area. The intersection perimeter between the conductors directs the breakdown of the dielectric material, increasing the likelihood that the programming event will be successful. In at least one embodiment, the portion of a current path that travels through a highly doped area is increased while the portion that travels through a non-highly doped area is decreased. This decreases post-program resistance, leading to better response time for the device.
摘要翻译：公开了一种在第一导体的边缘区域和第二导体的部分之间具有增加的相交周界的半导体器件。在一个实施例中，相交周界是栅极结构的周边与有效区域重叠的区域。导体之间的交叉点周界引导电介质材料的击穿，增加编程事件成功的可能性。在至少一个实施例中，穿过高掺杂区域的电流路径的部分增加，而穿过非高掺杂区域的部分减小。这降低了程序后阻抗，导致设备响应时间更长。

79. 发明授权

US07217604B2 Structure and method for thin box SOI device 有权
标题翻译：薄盒SOI器件的结构和方法
公开(公告)号：US07217604B2
公开(公告)日：2007-05-15
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

80. 发明授权

US07102204B2 Integrated SOI fingered decoupling capacitor 有权
标题翻译：集成SOI指法去耦电容
公开(公告)号：US07102204B2
公开(公告)日：2006-09-05
申请号：US10710256
申请日：2004-06-29
申请人： Zachary E. Berndlmaier , Edward W. Kiewra , Carl J. Radens , William R. Tonti
发明人： Zachary E. Berndlmaier , Edward W. Kiewra , Carl J. Radens , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1087 , H01L27/1203
摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.
摘要翻译：本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物，具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

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