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71. 发明申请

US20170324420A1 WIDEBAND POLAR RECEIVER ARCHITECTURE AND SIGNAL PROCESSING METHODS 审中-公开
公开(公告)号：US20170324420A1
公开(公告)日：2017-11-09
申请号：US15614560
申请日：2017-06-05
申请人： Innophase Inc.
发明人： Yang Xu , Sara Munoz Hermoso , Roc Berenguer Perez
IPC分类号： H03L7/24 , H04L27/22 , H04B1/16
CPC分类号： H03L7/24 , H03D3/007 , H03D2200/006 , H04L27/389
摘要： Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

72. 发明授权

US09497055B2 Method and apparatus for polar receiver with digital demodulation 有权
标题翻译：具有数字解调功能的极地接收机的方法和装置
公开(公告)号：US09497055B2
公开(公告)日：2016-11-15
申请号：US14634525
申请日：2015-02-27
申请人： Innophase Inc.
发明人： Yang Xu , Sara Munoz Hermoso , Roc Berenguer Perez
IPC分类号： H04L27/00 , G06F3/033 , H04L27/22 , H04B1/06 , G01S13/70
CPC分类号： H04L27/22 , G01S13/70 , H04B1/06
摘要： Circuitry and methods are described for digital signal demodulation. In a polar receiver, a modulated radio-frequency input signal is provided to frequency division circuitry, which may include a harmonic injection-locked oscillator (ILO). The phase of the frequency-divided output is measured using a self-triggered time-to-digital converter (TDC), which may be a Vernier TDC. A subtractor subtracts a period offset from the output of the TDC to generate an offset digital time output, and a digital integrator integrates the offset digital time output. The integrated time signal represents the phase of the radio-frequency input signal and can be used to determine a symbol, such as a phase-shift keying (PSK) or quadrature amplitude modulation (QAM) symbol, conveyed by the modulated radio-frequency input signal.
摘要翻译：电路和方法描述为数字信号解调。在极地接收机中，将调制的射频输入信号提供给分频电路，其可以包括谐波注入锁定振荡器（ILO）。使用可以是游标TDC的自触发时间 - 数字转换器（TDC）来测量分频输出的相位。减法器从TDC的输出中减去偏移量以产生偏移数字时间输出，数字积分器对偏移数字时间输出进行积分。积分时间信号表示射频输入信号的相位，并且可以用于确定由调制的射频输入传送的诸如相移键控（PSK）或正交幅度调制（QAM）符号的符号信号。

73. 发明申请

US20160254934A1 METHOD AND APPARATUS FOR POLAR RECEIVER WITH DIGITAL DEMODULATION 有权
标题翻译：具有数字解调的极性接收机的方法和装置
公开(公告)号：US20160254934A1
公开(公告)日：2016-09-01
申请号：US14634525
申请日：2015-02-27
申请人： Innophase Inc.
发明人： Yang Xu , Sara Munoz Hermoso , Roc Berenguer Perez
IPC分类号： H04L27/22 , H04B1/06
CPC分类号： H04L27/22 , G01S13/70 , H04B1/06
摘要： Circuitry and methods are described for digital signal demodulation. In a polar receiver, a modulated radio-frequency input signal is provided to frequency division circuitry, which may include a harmonic injection-locked oscillator (ILO). The phase of the frequency-divided output is measured using a self-triggered time-to-digital converter (TDC), which may be a Vernier TDC. A subtractor subtracts a period offset from the output of the TDC to generate an offset digital time output, and a digital integrator integrates the offset digital time output. The integrated time signal represents the phase of the radio-frequency input signal and can be used to determine a symbol, such as a phase-shift keying (PSK) or quadrature amplitude modulation (QAM) symbol, conveyed by the modulated radio-frequency input signal.
摘要翻译：电路和方法描述为数字信号解调。在极地接收机中，将调制的射频输入信号提供给分频电路，其可以包括谐波注入锁定振荡器（ILO）。使用可以是游标TDC的自触发时间 - 数字转换器（TDC）来测量分频输出的相位。减法器从TDC的输出中减去偏移量以产生偏移数字时间输出，数字积分器对偏移数字时间输出进行积分。积分时间信号表示射频输入信号的相位，并且可以用于确定由调制的射频输入传送的诸如相移键控（PSK）或正交幅度调制（QAM）符号的符号信号。

74. 发明申请

US20160004265A1 RADIO FREQUENCY PEAK DETECTION WITH SUBTHRESHOLD BIASING 有权
标题翻译：无线电频率峰值检测与底层偏移
公开(公告)号：US20160004265A1
公开(公告)日：2016-01-07
申请号：US14321299
申请日：2014-07-01
申请人： Innophase Inc.
发明人： Nicolo Testi , Xi Li , Yang Xu
IPC分类号： G05F1/46 , H03K3/012 , H03H11/04
CPC分类号： G05F1/46
摘要： A radio-frequency peak amplitude detection circuit includes a load capacitor, a current source that charges the load capacitor and set the bias current for the field effect transistors, and a pair of field effect transistors. The gates of the field effect transistors are biased at a level below the threshold voltage of the transistors. The transistors are arranged in parallel with the capacitor and are operable to drain the capacitor at a rate determined by a differential input at the gates of the transistors. The voltage across the load capacitor is low-pass filtered and has a voltage level representative of the amplitude of the differential input signal.
摘要翻译：射频峰值振幅检测电路包括负载电容器，对负载电容器充电并为场效应晶体管设置偏置电流的电流源以及一对场效应晶体管。场效应晶体管的栅极被偏置在低于晶体管的阈值电压的电平。晶体管与电容器并联布置，并且可操作地以由晶体管的栅极处的差分输入确定的速率来排出电容器。负载电容器两端的电压被低通滤波，并具有代表差分输入信号振幅的电压电平。

75. 发明授权

US09024696B2 Digitally controlled injection locked oscillator 有权
标题翻译：数字控制注入锁定振荡器
公开(公告)号：US09024696B2
公开(公告)日：2015-05-05
申请号：US13840379
申请日：2013-03-15
申请人： Innophase, Inc.
发明人： Xi Li , Yang Xu
IPC分类号： H03B5/12
CPC分类号： H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/007 , H03B2200/0074 , H03B2201/0208 , H03B2201/0291 , H03D3/22
摘要： An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio.
摘要翻译：一种注入锁定振荡器（ILO），包括具有数字控制电容器组的振荡电路，耦合到所述振荡电路的交叉耦合差分晶体管对，至少一个信号注入节点和至少一个输出节点，所述至少一个输出节点被配置为提供注入锁定输出信号; 数字控制注入比电路，具有耦合到所述至少一个信号注入节点的注入输出，被配置为接受输入信号并产生施加到所述至少一个注入节点的可调注入信号; 以及连接到所述电容器组的ILO控制器和所述注入比电路，所述注入比电路被配置为向所述电容器组施加控制信号以调整所述电容器组的谐振频率，并且向所述注入比电路施加控制信号以调整信号注入比。

76. 发明申请

US20140270003A1 Polar Receiver Architecture and Signal Processing Methods 有权
标题翻译：极地接收机架构和信号处理方法
公开(公告)号：US20140270003A1
公开(公告)日：2014-09-18
申请号：US13840478
申请日：2013-03-15
申请人： INNOPHASE, INC.
发明人： Yang Xu , Sara Munoz Hermoso
IPC分类号： H03D3/00 , H04L27/227
CPC分类号： H03D3/007 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03D1/22 , H03D5/00 , H04L27/227 , H04L27/2272 , H04L27/389
摘要： Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.
摘要翻译：用二次谐波注入锁定振荡器压缩接收到的调制信号的可变相位分量，并用基本注入锁定振荡器产生延迟相位压缩信号，并组合相位压缩信号和延迟相位压缩信号以获得估计的可变相位分量的导数，并且进一步处理估计的导数以恢复包含在接收的调制信号内的数据。

77. 发明申请

US20140266480A1 Digitally Controlled Injection Locked Oscillator 有权
标题翻译：数字控制注入锁定振荡器
公开(公告)号：US20140266480A1
公开(公告)日：2014-09-18
申请号：US13840379
申请日：2013-03-15
申请人： INNOPHASE, INC.
发明人： Xi Li , Yang Xu
IPC分类号： H03K3/36
CPC分类号： H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/007 , H03B2200/0074 , H03B2201/0208 , H03B2201/0291 , H03D3/22
摘要： An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio.
摘要翻译：一种注入锁定振荡器（ILO），包括具有数字控制电容器组的振荡电路，耦合到所述振荡电路的交叉耦合差分晶体管对，至少一个信号注入节点和至少一个输出节点，所述至少一个输出节点被配置为提供注入锁定输出信号; 数字控制注入比电路，具有耦合到所述至少一个信号注入节点的注入输出，被配置为接受输入信号并产生施加到所述至少一个注入节点的可调注入信号; 以及连接到所述电容器组的ILO控制器和所述注入比电路，所述注入比电路被配置为向所述电容器组施加控制信号以调整所述电容器组的谐振频率，并且向所述注入比电路施加控制信号以调整信号注入比。

78. 发明申请

US20140185708A1 Single-Bit Direct Modulation Transmitter 有权
标题翻译：单位直接调制变送器
公开(公告)号：US20140185708A1
公开(公告)日：2014-07-03
申请号：US13842470
申请日：2013-03-15
申请人： INNOPHASE, INC.
发明人： Yang Xu , Xuejun Zhang
IPC分类号： H04L25/03
CPC分类号： H04L25/03834 , H03M1/685 , H04L25/0384 , H04L27/34
摘要： Single-bit transmitter modulator having a digital pulse shaping filter configured to shape data pulses of an inphase signal and quadrature signal; an upsampling filter configured to increase the sample rate of the inphase signal and quadrature signal; a sigma-delta modulator providing a one-bit inphase output signal and a one-bit quadrature output signal; an inphase low-order analog low pass filter coupling the one-bit inphase output signal to an inphase channel input of a quadrature modulator, and a quadrature low-order analog low pass filter coupling the one-bit quadrature output signal to a quadrature channel input of a quadrature modulator; and, wherein the quadrature modulator is connected to a carrier signal generator and is configured to generate an inphase and quadrature modulated carrier.
摘要翻译：具有数字脉冲整形滤波器的单位发射调制器，被配置为对同相信号和正交信号的数据脉冲进行整形; 上采样滤波器，被配置为增加同相信号和正交信号的采样率; 提供一位同相输出信号和一位正交输出信号的Σ-Δ调制器; 将一位同相输出信号耦合到正交调制器的同相通道输入的同相低阶模拟低通滤波器，以及正交低阶模拟低通滤波器，将一位正交输出信号耦合到正交通道输入的正交调制器; 并且其中所述正交调制器连接到载波信号发生器并被配置为产生同相和正交调制载波。

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