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71. 发明授权

US07281115B2 Method, system and program product for clearing selected storage translation buffer entries 有权
标题翻译：清除所选存储转换缓冲区条目的方法，系统和程序产品
公开(公告)号：US07281115B2
公开(公告)日：2007-10-09
申请号：US11204321
申请日：2005-08-15
申请人： Timothy J. Siegel , Lisa C. Heller , Erwin F. Pfeffer , Kenneth E. Plambeck
发明人： Timothy J. Siegel , Lisa C. Heller , Erwin F. Pfeffer , Kenneth E. Plambeck
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
摘要翻译：提供指令来执行与特定地址空间相关联的所选地址转换缓冲器条目（TLB条目）的清除，诸如存储段或存储区域。缓冲区条目与段表项或区域表项或ASCE地址相关。该指令可以通过软件仿真，硬件，固件或其组合来实现。

72. 发明授权

US09086886B2 Method and apparatus to limit millicode routine end branch prediction 有权
标题翻译：终止分支预测的方法和装置
公开(公告)号：US09086886B2
公开(公告)日：2015-07-21
申请号：US12821690
申请日：2010-06-23
申请人： Brian R. Prasky , James J. Bonanno , Lisa C. Heller
发明人： Brian R. Prasky , James J. Bonanno , Lisa C. Heller
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/3017
摘要： A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines.
摘要翻译：一个计算系统方法，程序和硬件相关的millicode预测与特定的millicode例程接收架构式的代码，并将millicode存储在内部存储器中。计算机系统处理器的流水线用于预测和选择分支目标缓冲器（BTB）目标地址。一种计算机微码控制，其使得能够使用毫秒代码程序的多个用户程序之间的操作系统（O / S）多任务控制，并且通过使用分支目标缓冲器（BTB）预测来确保程序不相互干扰分支目标，以确保毫秒代码程序在执行所述毫代码路由所要求的操作之前不会从所述毫代码程序外部获取，所述分支目标缓冲器预测采用用于预测毫米编码的分支毫代数条目和毫分节结束指令的相关机制，并且用于关联millicode 用特定的millicode例程结束预测。

73. 发明授权

US08595469B2 Diagnose instruction for serializing processing 有权
公开(公告)号：US08595469B2
公开(公告)日：2013-11-26
申请号：US12822886
申请日：2010-06-24
申请人： Lisa C. Heller
发明人： Lisa C. Heller
IPC分类号： G06F9/00
CPC分类号： G06F9/30087 , G06F9/30003 , G06F9/30079 , G06F9/30185 , G06F9/45533 , G06F9/52
摘要： A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.

74. 发明授权

US08572624B2 Providing multiple quiesce state machines in a computing environment 有权
标题翻译：在计算环境中提供多个静默状态机
公开(公告)号：US08572624B2
公开(公告)日：2013-10-29
申请号：US12037734
申请日：2008-02-26
申请人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46 , G06F7/38
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译：一种用于提供多个静默状态机的系统，方法和计算机程序产品。该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。因此，多个静默请求可能在系统中同时处于活动状态。

75. 发明授权

US08140834B2 System, method and computer program product for providing a programmable quiesce filtering register 失效
标题翻译：用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品
公开(公告)号：US08140834B2
公开(公告)日：2012-03-20
申请号：US12037808
申请日：2008-02-26
申请人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Jennifer A. Navarro , Timothy J. Slegel
发明人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Jennifer A. Navarro , Timothy J. Slegel
IPC分类号： G06F9/48 , G06F9/52
CPC分类号： G06F9/4812
摘要： A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.
摘要翻译：一种用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品。该方法包括在处理器处接收静止中断请求。处理器正在以一种模式执行。识别与该模式相关联的过滤区域。确定处理器是否可以过滤停顿中断请求。该确定响应于过滤区域和可编程过滤寄存器的内容，用于指示接收处理器执行的过滤异常。响应于确定可以对请求进行过滤，过滤掉静默中断请求。

76. 发明申请

US20110320791A1 Method and Apparatus to Limit Millicode Routine End Branch Prediction 有权
标题翻译：限制Millicode常规结束分支预测的方法和装置
公开(公告)号：US20110320791A1
公开(公告)日：2011-12-29
申请号：US12821690
申请日：2010-06-23
申请人： Brian R. Prasky , James J. Bonanno , Lisa C. Heller
发明人： Brian R. Prasky , James J. Bonanno , Lisa C. Heller
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3017
摘要： A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines.
摘要翻译：一个计算系统方法，程序和硬件相关的millicode预测与特定的millicode例程接收架构式的代码，并将millicode存储在内部存储器中。计算机系统处理器的流水线用于预测和选择分支目标缓冲器（BTB）目标地址。一种计算机微码控制，其使得能够使用毫秒代码程序的多个用户程序之间的操作系统（O / S）多任务控制，并且通过使用分支目标缓冲器（BTB）预测来确保程序不相互干扰分支目标，以确保毫秒代码程序在执行所述毫代码路由所要求的操作之前不会从所述毫代码程序外部获取，所述分支目标缓冲器预测采用用于预测毫米编码的分支毫代数条目和毫分节结束指令的相关机制，并且用于关联millicode 用特定的millicode例程结束预测。

77. 发明授权

US07890731B2 Clearing selected storage translation buffer entries based on table origin address 有权
标题翻译：根据表起始地址清除所选存储转换缓冲区条目
公开(公告)号：US07890731B2
公开(公告)日：2011-02-15
申请号：US11733224
申请日：2007-04-10
申请人： Timothy J. Slegel , Lisa C. Heller , Erwin F. Pfeffer , Kenneth E. Plambeck
发明人： Timothy J. Slegel , Lisa C. Heller , Erwin F. Pfeffer , Kenneth E. Plambeck
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/3824 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/683
摘要： An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
摘要翻译：提供指令来执行与特定地址空间相关联的所选地址转换缓冲器条目（TLB条目）的清除，诸如存储段或存储区域。缓冲区条目与段表项或区域表项或ASCE地址相关。该指令可以通过软件仿真，硬件，固件或其组合来实现。

78. 发明申请

US20090210650A1 METHOD FOR SERIALIZING TRANSLATION LOOKASIDE BUFFER ACCESS AROUND ADDRESS TRANSLATION PARAMETER MODIFICATION 有权
标题翻译：串行翻译查询缓冲区访问方法地址转换参数修改方法
公开(公告)号：US20090210650A1
公开(公告)日：2009-08-20
申请号：US12032178
申请日：2008-02-15
申请人： Gregory W. Alexander , Lisa C. Heller , Chung-Lung Kevin Shum
发明人： Gregory W. Alexander , Lisa C. Heller , Chung-Lung Kevin Shum
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F2212/684
摘要： Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided.
摘要翻译：本发明的实施例包括一种在包括翻译后备缓冲器的处理器中同步翻译改变的方法，所述方法包括设置控制位以使得能够阻止错过所述翻译后备缓冲器的所有提取请求，而不改变当前进程的转换状态; 如果存在至少一个未完成的翻译，则等待完成至少一个等待翻译; 并重置控制位。提供处理器和计算机程序产品。

79. 发明授权

US06996698B2 Blocking processing restrictions based on addresses 有权
标题翻译：基于地址的阻塞处理限制
公开(公告)号：US06996698B2
公开(公告)日：2006-02-07
申请号：US10435961
申请日：2003-05-12
申请人： Timothy J. Slegel , Jane H. Bartik , Lisa C. Heller , Erwin F. Pfeffer , Ute Gaertner
发明人： Timothy J. Slegel , Jane H. Bartik , Lisa C. Heller , Erwin F. Pfeffer , Ute Gaertner
IPC分类号： G06F12/00
CPC分类号： G06F12/1475 , G06F12/1036
摘要： Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that fetching of storage keys is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of addresses, which indicates whether the fetching can continue. If fetching can continue, the restriction is ignored.
摘要翻译：在某些情况下，计算环境的处理限制被过滤和阻止，使处理继续，尽管有限制。一个限制包括响应于缓冲区未命中而禁止取出存储密钥的指示。当计算环境的处理单元满足该限制时，它执行地址的比较，其指示获取是否可以继续。如果提取可以继续，限制将被忽略。

80. 发明授权

US5619715A Hardware implementation of string instructions 失效
标题翻译：硬件实现字符串指令
公开(公告)号：US5619715A
公开(公告)日：1997-04-08
申请号：US452638
申请日：1995-05-25
申请人： Robert M. Dinkjian , Lisa C. Heller , Steven R. Kordus , Kenneth A. Lauricella , Thomas W. Seigendall , Robert A. Skaggs , Nelson S. Xu
发明人： Robert M. Dinkjian , Lisa C. Heller , Steven R. Kordus , Kenneth A. Lauricella , Thomas W. Seigendall , Robert A. Skaggs , Nelson S. Xu
IPC分类号： G06F7/02 , G06F7/74 , G06F9/308 , G06F7/00
CPC分类号： G06F7/74 , G06F7/026 , G06F9/30018
摘要： A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string. The offset is used to shift the byte count mask by a number of positions corresponding to the position of the first byte of the string and inserts 0s in the byte count mask for positions not belonging to the string. A byte-by-byte comparator determines string end conditions and provides an output word with a significant bit indication for each byte for which an end condition has been detected. The output of the byte-by-byte comparator is combined with the shifted byte count mask, and the result is decoded by means of a prioritized decoder which generates a string write mask.
摘要翻译：数据处理器处理来自存储器的数据串，其中数据串不开始或在存储器边界处结束。字符串在存储器中由起始地址定义，定义字符串总字节数的字节数以及定义起始地址位置中第一个字节的位置的字节偏移量。处理器存储字节计数，并在处理每个多字节字时减少字节计数。字节计数掩码电路产生一个字节计数掩码，每个字节计数的字节数大于每个存储字的字节数。当待处理的剩余字节数低于存储器字中的字节数时，字节计数掩码仅针对与最后一个存储器字中字符串的字节位置相对应的位置产生1。偏移寄存器存储定义字符串的第一个存储字中第一个字节的位置的偏移量。偏移用于将字节计数掩码移位与字符串的第一个字节的位置相对应的位置数，并将不属于字符串的位置插入到字节计数掩码中的0。逐字节比较器确定字符串结束条件，并为已经检测到结束条件的每个字节提供具有有效位指示的输出字。逐字节比较器的输出与移位的字节计数掩码组合，结果通过生成字符串写掩码的优先级解码器进行解码。

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