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71. 发明授权

US10019374B2 Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system 有权
公开(公告)号：US10019374B2
公开(公告)日：2018-07-10
申请号：US15141030
申请日：2016-04-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/0893 , G06F12/0891 , G06F9/30 , G06F9/38 , G06F12/0897
CPC分类号： G06F12/0893 , G06F9/30 , G06F9/30043 , G06F9/30087 , G06F9/3009 , G06F9/3836 , G06F9/3838 , G06F12/0891 , G06F12/0897 , G06F2212/1024 , G06F2212/60
摘要： A technique for operating a lower level cache memory of a data processing system includes receiving an operation that is associated with a first thread. Logical partition (LPAR) information for the operation is used to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.

72. 发明授权

US09959213B2 Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system 有权
公开(公告)号：US09959213B2
公开(公告)日：2018-05-01
申请号：US15141013
申请日：2016-04-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/0897 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0897 , G06F9/30 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3009 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F2212/60
摘要： A technique for operating a lower level cache memory of a data processing system includes receiving, by a store queue controller, an operation that is associated with a first thread. The store queue controller uses level one (L1) cache memory miss information for the operation to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.

73. 发明授权

US09928119B2 Translation entry invalidation in a multithreaded data processing system 有权
公开(公告)号：US09928119B2
公开(公告)日：2018-03-27
申请号：US15082830
申请日：2016-03-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Derek E. Williams
IPC分类号： G06F9/34 , G06F12/10 , G06F9/52 , G06F9/38 , G06F12/1027
CPC分类号： G06F9/524 , G06F9/30047 , G06F9/30087 , G06F9/3834 , G06F9/522 , G06F12/1027 , G06F2212/1016 , G06F2212/683
摘要： In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

74. 发明授权

US09910782B2 Expedited servicing of store operations in a data processing system 有权
公开(公告)号：US09910782B2
公开(公告)日：2018-03-06
申请号：US14839241
申请日：2015-08-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/08 , G06F9/30 , G06F12/0875 , G06F12/0888
CPC分类号： G06F12/0875 , G06F9/30043 , G06F9/3824 , G06F12/0888 , G06F12/0895 , G06F2212/303 , G06F2212/452 , G06F2212/6022
摘要： In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to the store instruction being marked as high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

75. 发明授权

US09824014B2 Expedited servicing of store operations in a data processing system 有权
公开(公告)号：US09824014B2
公开(公告)日：2017-11-21
申请号：US14871696
申请日：2015-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/08 , G06F9/48 , G06F9/38 , G06F12/0842 , G06F12/0811 , G06F12/0831 , G06F12/0875
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/48 , G06F12/0811 , G06F12/0831 , G06F12/0875 , G06F2212/283 , G06F2212/452 , G06F2212/621
摘要： In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

76. 发明授权

US09652399B2 Expedited servicing of store operations in a data processing system 有权
公开(公告)号：US09652399B2
公开(公告)日：2017-05-16
申请号：US14871709
申请日：2015-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/0875 , G06F12/0888 , G06F17/30 , G06F11/14
CPC分类号： G06F12/0875 , G06F9/30043 , G06F11/1461 , G06F11/1464 , G06F12/0888 , G06F17/30351 , G06F17/30371 , G06F2209/5019 , G06F2212/303 , G06F2212/452 , G06F2212/6022
摘要： In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.

77. 发明授权

US09514083B1 Topology specific replicated bus unit addressing in a data processing system 有权
公开(公告)号：US09514083B1
公开(公告)日：2016-12-06
申请号：US14960507
申请日：2015-12-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard L. Arndt , Florian Auernhammer , Hugh Shen , Derek E. Williams
IPC分类号： G06F13/40 , G06F13/28 , G06F13/24 , G06F12/08 , G06F9/54 , G06F9/38 , G06F9/30
CPC分类号： G06F13/404 , G06F9/3004 , G06F9/30043 , G06F9/3891 , G06F9/544 , G06F12/0815 , G06F12/0875 , G06F12/0888 , G06F13/24 , G06F13/28 , G06F13/364 , G06F13/4282 , G06F2212/1056 , G06F2212/452
摘要： A technique for handling cache-inhibited operations in a data processing system includes receiving, at a replicated bus unit, a cache-inhibited (CI) operation. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is associated with the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being associated with the replicated bus unit, the replicated bus unit processes the CI operation. In response to the address associated with the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being associated with the replicated bus unit, the replicated bus unit ignores the CI operation.

78. 发明授权

US09514045B2 Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system 有权
标题翻译：在弱有序的记忆体系中实施有效支持累积性的障碍的技术
公开(公告)号：US09514045B2
公开(公告)日：2016-12-06
申请号：US14245156
申请日：2014-04-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F9/312 , G06F9/52 , G06F12/00 , G06F12/08 , G06F12/12 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/522 , G06F12/0815 , G06F12/0842 , G06F12/0897 , G06F12/128 , G06F2212/284 , G06F2212/6042
摘要： A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory. Dependencies in a dependency data structure of a store queue of the cache memory are set based on the pollution vectors to reduce unnecessary ordering effects. Store operations are dispatched from the store queue in accordance with the dependencies indicated by the dependency data structure.
摘要翻译：用于操作数据处理系统的高速缓冲存储器的技术包括创建相应的污染向量，以跟踪由相关联的处理器核心执行的多个并发线程当前被驻留在高速缓存存储器中的存储操作所污染的哪一个。基于污染向量设置缓存存储器的存储队列的依赖性数据结构中的依赖关系，以减少不必要的排序效应。存储操作根据依赖关系数据结构指示的依赖关系从存储队列中发出。

79. 发明授权

US09430380B2 Managing memory transactions in a distributed shared memory system supporting caching above a point of coherency 有权
公开(公告)号：US09430380B2
公开(公告)日：2016-08-30
申请号：US14312157
申请日：2014-06-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0817 , G06F12/0828 , G06F12/0833 , G06F2212/283 , G06F2212/62
摘要： In response to execution in a memory transaction of a transactional load instruction that speculatively binds to a value held in a store-through upper level cache, a processor core sets a flag, transmits a transactional load operation to a store-in lower level cache that tracks a target cache line address of a target cache line containing the value, monitors, during a core TM tracking interval, the target cache line address for invalidation messages from the store-in lower level cache until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the target cache line address, and responsive to receipt during the core TM tracking interval of an invalidation message indicating presence of a conflicting snooped operation, resets the flag. At termination of the memory transaction, the processor core fails the memory transaction responsive to the flag being reset.

80. 发明授权

US09396127B2 Synchronizing access to data in shared memory 有权
标题翻译：同步访问共享内存中的数据
公开(公告)号：US09396127B2
公开(公告)日：2016-07-19
申请号：US14192227
申请日：2014-02-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0811 , G06F12/0833 , G06F2212/283 , G06F2212/601 , G06F2212/621
摘要： In some embodiments, in response to execution of a load-reserve instruction that binds to a load target address held in a store-through upper level cache, a processor core sets a core reservation flag, transmits a load-reserve operation to a store-in lower level cache, and tracks, during a core reservation tracking interval, the reservation requested by the load-reserve operation until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the reservation. In response to receipt during the core reservation tracking interval of an invalidation signal indicating presence of a conflicting snooped operation, the processor core cancels the reservation by resetting the core reservation flag and fails a subsequent store-conditional operation. Responsive to not canceling the reservation during the core reservation tracking interval, the processor core determines whether a store-conditional operation succeeds by reference to a pass/fail indication provided by the store-in lower level cache.
摘要翻译：在一些实施例中，响应于绑定到存储在上层高速缓存中的加载目标地址的负载预留指令的执行，处理器核心设置核心预留标志，向存储 - 在低级缓存中，并且在核心预约跟踪间隔期间跟踪由加载备用操作请求的预留，直到存储的较低级缓存信号指示存储的较低级缓存已经承担了跟踪该预留的责任。响应于在指示存在冲突的窥探操作的无效信号的核心预约跟踪间隔期间的接收，处理器核心通过重置核心预留标志来取消预约，并且使随后的存储条件操作失败。响应于在核心预约跟踪间隔期间不取消预约，处理器核心通过参考由存储的下级高速缓存提供的通过/失败指示来确定存储条件操作是否成功。

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