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71. 发明申请

US20140239420A1 SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION 有权
标题翻译：硅酸盐浇筑通过植入
公开(公告)号：US20140239420A1
公开(公告)日：2014-08-28
申请号：US13776324
申请日：2013-02-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Veeraraghavan S. Basker , Sanjay Mehta , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803
摘要： A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.
摘要翻译：一种形成FinFET结构的方法，其包括在半导体衬底上形成翅片; 形成围绕所述翅片中的至少一个包围的门，所述门具有面对所述翅片的第一表面和相对的第二表面; 在门的顶部沉积硬掩模; 将氮注入到栅极的第一和第二表面中，以便在栅极中形成含氮层，该栅极位于门的顶部以下且与硬掩模直接接触; 在栅极上形成间隔物并与含氮层接触; 并且在所述至少一个翅片上外延地沉积硅以形成升高的源极/漏极。还公开了FinFET结构。

72. 发明申请

US20140239395A1 CONTACT RESISTANCE REDUCTION IN FINFETS 审中-公开
标题翻译： FINFET中的接触电阻降低
公开(公告)号：US20140239395A1
公开(公告)日：2014-08-28
申请号：US13775946
申请日：2013-02-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , STMicroelectronics, Inc.
发明人： Veeraraghavan S. Basker , Qing Liu , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/41791 , H01L29/165 , H01L29/456 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method for forming contacts in a semiconductor device includes forming a plurality of substantially parallel semiconductor fins on a dielectric layer of a substrate having a gate structure formed transversely to a longitudinal axis of the fins. The fins are merged by epitaxially growing a crystalline material between the fins. A field dielectric layer is deposited over the fins and the crystalline material. Trenches that run transversely to the longitudinal axis of the fins are formed to expose the fins in the trenches. An interface layer is formed over portions of the fins exposed in the trenches. Contact lines are formed in the trenches that contact a top surface of the interface layer on the fins and at least a portion of side surfaces of the interface layer on the fins.
摘要翻译：一种用于在半导体器件中形成触点的方法包括在具有横向于鳍的纵向轴线形成的栅极结构的基底的介电层上形成多个基本上平行的半导体鳍。翅片通过在翅片之间外延生长结晶材料而合并。场致电介质层沉积在鳍片和结晶材料上。形成横向于翅片的纵向轴线的沟槽以暴露沟槽中的翅片。界面层形成在暴露在沟槽中的翅片的部分上。接触线形成在与鳍片上的界面层的顶表面和鳍片上界面层的至少一部分侧表面接触的沟槽中。

73. 发明授权

US08815661B1 MIM capacitor in FinFET structure 有权
标题翻译： MIM电容器在FinFET结构
公开(公告)号：US08815661B1
公开(公告)日：2014-08-26
申请号：US13768248
申请日：2013-02-15
申请人： International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Effendi Leobandung , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/1211 , H01L28/40 , H01L29/66795
摘要： A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride. A polysilicon layer is deposited over the metal-insulator-metal capacitor followed by etching back the polysilicon layer and the metal-insulator-metal capacitor layers from ends of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer. A spacer may be formed on surfaces facing the ends of the silicon fins followed by the formation of epitaxial silicon over the ends of the silicon fins. Also disclosed is a FinFET structure having a metal-insulator-metal capacitor.
摘要翻译：一种形成具有金属 - 绝缘体 - 金属电容器的FinFET结构的方法。在半导体衬底上形成硅翅片，然后通过沉积第一层氮化钛，介电层和第二层氮化钛的顺序层，在硅散热片上形成金属 - 绝缘体 - 金属电容器。在金属 - 绝缘体 - 金属电容器上沉积多晶硅层，随后从硅散热片的端部刻蚀多晶硅层和金属 - 绝缘体 - 金属电容器层，使得硅片的第一和第二端从多晶硅突出层。可以在面对硅散热片的端部的表面上形成间隔物，随后在硅散热片的端部上形成外延硅。还公开了具有金属 - 绝缘体 - 金属电容器的FinFET结构。

74. 发明申请

US20140131802A1 Structure and Method to Form Passive Devices in ETSOI Process Flow 有权
标题翻译：在ETSOI流程中形成被动设备的结构和方法
公开(公告)号：US20140131802A1
公开(公告)日：2014-05-15
申请号：US14159027
申请日：2014-01-20
申请人： International Business Machines Corporation
发明人： Ming Cai , Dechao Guo , Chun-Chen Yeh
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/13
摘要： Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.
摘要翻译：提供了在极薄的绝缘体上硅（ETSOI）晶圆上制造无源器件的技术。在一方面，提供了一种用于在ETSOI晶片中制造一个或多个无源器件的方法。该方法包括以下步骤。提供具有衬底的ETSOI晶片和通过掩埋氧化物（BOX）与衬底分离的ETSOI层。 ETSOI层涂有保护层。形成延伸穿过保护层，ETSOI层和BOX的至少一个沟槽，并且其中衬底的一部分暴露在沟槽内。在沟槽的侧壁上形成间隔物。从衬底模板化的外延硅在沟槽中生长。保护层从ETSOI层去除。无源器件形成在外延硅中。

75. 发明申请

US20140110785A1 REPLACEMENT METAL GATE FINFET 有权
标题翻译：更换金属门FINFET
公开(公告)号：US20140110785A1
公开(公告)日：2014-04-24
申请号：US13672899
申请日：2012-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Hemanth Jagannathan , Sanjay C. Mehta , Junli Wang , Chun-Chen Yeh , Stefan Schmitz
IPC分类号： H01L29/78
CPC分类号： H01L21/28132 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
摘要翻译：场效应晶体管器件包括鳍状物，其包括布置在绝缘体层上的半导体材料，鳍包括沟道区，部分地布置在鳍的沟道区上的硬掩模层，布置在硬掩模层上并在沟道上方的栅叠层翅片的区域，布置在硬掩模层的第一部分上的金属合金层，邻近栅极堆叠布置的金属合金层，以及邻近栅极堆叠并在金属合金层上方布置的第一间隔物。

76. 发明授权

US08673729B1 finFET eDRAM strap connection structure 有权
标题翻译： finFET eDRAM带连接结构
公开(公告)号：US08673729B1
公开(公告)日：2014-03-18
申请号：US13705477
申请日：2012-12-05
申请人： International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Effendi Leobandung , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L29/76
CPC分类号： H01L24/40 , H01L21/845 , H01L24/37 , H01L27/1082 , H01L27/10826 , H01L27/10867 , H01L27/1087 , H01L27/10879 , H01L27/1211 , H01L29/66181 , H01L29/945 , H01L2224/371 , H01L2924/00014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/84
摘要： A method of forming a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor comprises forming a buried oxide layer in a substrate, the buried oxide layer defining an SOI layer on a surface of the substrate; forming a deep trench through the SOI layer and the buried oxide layer in the substrate; forming a storage capacitor in a lower portion of the deep trench; conformally doping a sidewall of an upper portion of the deep trench; depositing a metal strap on the conformally doped sidewall and on the storage capacitor; forming at least one fin in the SOI layer, the fin being in communication with the metal strap; forming a spacer over the metal strap and over a juncture of the fin and the metal strap; and depositing a passive word line on the spacer.
摘要翻译：形成用于将嵌入式动态随机存取存储器（eDRAM）连接到晶体管的带连接结构的方法包括在衬底中形成掩埋氧化物层，所述掩埋氧化物层在衬底的表面上限定SOI层; 通过SOI层和衬底中的掩埋氧化物层形成深沟槽; 在深沟槽的下部形成存储电容器; 保形地掺杂深沟槽的上部的侧壁; 在保形掺杂侧壁和存储电容器上沉积金属带; 在所述SOI层中形成至少一个翅片，所述翅片与所述金属带连通; 在所述金属带上并且在所述翅片和所述金属带的接合部上方形成隔离物; 并在隔离物上沉积被动字线。

77. 发明申请

US20130154006A1 FINFET WITH VERTICAL SILICIDE STRUCTURE 有权
标题翻译： FINFET与垂直硅胶结构
公开(公告)号：US20130154006A1
公开(公告)日：2013-06-20
申请号：US13649284
申请日：2012-10-11
申请人： International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Chung-Hsun Lin , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1211 , H01L29/0649 , H01L29/41791 , H01L29/45 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.
摘要翻译： FinFET和用于制造具有垂直硅化物结构的FinFET的方法。一种方法包括提供具有多个翅片的基板，在基板上形成栅极堆叠，其中栅极堆叠具有至少一个侧壁并形成邻近栅极堆叠侧壁的偏置间隔物。该方法还包括生长外延膜，其将翅片合并以形成外延合并层，形成与偏置间隔物的至少一部分相邻的场氧化物层，并去除场氧化物层的一部分以暴露部分的外延合并层。该方法还包括去除外延合并层的暴露部分的至少一部分以形成外延合并侧壁和外延合并间隔区，并在外延合并侧壁内形成硅化物以形成硅化物层和二硅化物侧壁

78. 发明公开

US20240072164A1 VTFET WITH CONTROLLED FIN HEIGHT 审中-公开
公开(公告)号：US20240072164A1
公开(公告)日：2024-02-29
申请号：US17823799
申请日：2022-08-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong Xie , Chun-Chen Yeh , Alexander Reznicek , Kangguo Cheng
IPC分类号： H01L29/78 , H01L29/08 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/0847 , H01L29/66553 , H01L29/66666
摘要： A semiconductor device includes: a vertical transport field-effect transistor (VTFET) device including a bottom source/drain (S/D) epitaxial layer, a vertical fin channel formed on the bottom S/D epitaxial layer, and a top S/D epitaxial layer formed on the vertical fin channel. The bottom S/D epitaxial layer has an asymmetric profile in cross-section where a first side of the vertical fin channel is aligned with a first side of the bottom S/D epitaxial layer, and the bottom S/D epitaxial layer has a stepped profile that extends beyond a second edge of the vertical fin channel.

79. 发明授权

US11239343B2 Vertical transistor including symmetrical source/drain extension junctions 有权
公开(公告)号：US11239343B2
公开(公告)日：2022-02-01
申请号：US16797097
申请日：2020-02-21
申请人： International Business Machines Corporation
发明人： Chun-Chen Yeh , Alexander Reznicek , Veeraraghavan Basker , Junli Wang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L21/223
摘要： A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

80. 发明申请

US20210296184A1 REDUCED SOURCE/DRAIN COUPLING FOR CFET 有权
公开(公告)号：US20210296184A1
公开(公告)日：2021-09-23
申请号：US16826879
申请日：2020-03-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong Xie , Alexander Reznicek , Chanro Park , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/06
摘要： A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.

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