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71. 发明授权

US08112574B2 Swappable sets of partial-mapping tables in a flash-memory system with a command queue for combining flash writes 有权
标题翻译：具有用于组合闪存写入的命令队列的闪存系统中的可转换的部分映射表
公开(公告)号：US08112574B2
公开(公告)日：2012-02-07
申请号：US12347306
申请日：2008-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G11C16/102 , G11C2216/30
摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.
摘要翻译：闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。映射所需的RAM大大降低。数据缓冲器存储一页主机写入数据。扇区写入使用数据缓冲区进行合并。当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个映射表。

72. 发明授权

US07966462B2 Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips 有权
标题翻译：具有平面交错顺序ECC的多通道闪存模块写入和背景回收到限制写入闪存芯片
公开(公告)号：US07966462B2
公开(公告)日：2011-06-21
申请号：US11871627
申请日：2007-10-12
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/02
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C16/0408 , G11C2211/5649
摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
摘要翻译：使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。还执行后台回收和ECC写入。

73. 发明授权

US07761653B2 Flash micro-controller with shadow boot-loader SRAM for dual-device booting of micro-controller and host 失效
标题翻译：闪存微控制器带有引导加载器的SRAM，用于微控制器和主机的双设备启动
公开(公告)号：US07761653B2
公开(公告)日：2010-07-20
申请号：US11875648
申请日：2007-10-19
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F9/441
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The boot code includes an initial boot loader, boot code and a control program that are executed by the flash microcontroller, and an operating system OS image and an external-host control program that are executed by an external host. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A first-reset-read address from the external host is captured by the microcontroller during its boot sequence and stored in a mapping table along with a physical address of the block in the SRAM buffer with the operating system OS image and the external-host control program. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导代码包括由闪存微控制器执行的初始引导加载程序，引导代码和控制程序，以及由外部主机执行的操作系统OS映像和外部主机控制程序。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。微控制器在其引导序列期间捕获来自外部主机的第一复位读取地址，并将其与SRAM缓冲器中具有操作系统OS映像和外部主机控制的块的物理地址一起存储在映射表中程序。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。

74. 发明授权

US07690030B1 Electronic data flash card with fingerprint verification capability 有权
标题翻译：具有指纹验证功能的电子数据闪存卡
公开(公告)号：US07690030B1
公开(公告)日：2010-03-30
申请号：US11458987
申请日：2006-07-20
申请人： Abraham C. Ma , Sun-Teck See , Charles C. Lee , Edward W. Lee , Ming-Shiang Shen
发明人： Abraham C. Ma , Sun-Teck See , Charles C. Lee , Edward W. Lee , Ming-Shiang Shen
IPC分类号： G06F7/04
CPC分类号： G06F12/1416 , G06F21/32 , G06F21/34 , G06F21/78 , G06K19/07 , G06K19/07354
摘要： An electronic data flash card with fingerprint capability is accessible by an host computer, and includes a processing unit connected to a flash memory device that stores a data file and reference fingerprint data of a person authorized to access the data file, a fingerprint sensor for scanning the fingerprint of a user and for generating input fingerprint data that can be compared with the stored reference fingerprint data, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer.
摘要翻译：具有指纹能力的电子数据闪存卡可由主机访问，并且包括连接到闪存设备的处理单元，该闪存设备存储被授权访问数据文件的人员的数据文件和参考指纹数据，用于扫描的指纹传感器用户的指纹和用于生成可以与存储的参考指纹数据进行比较的输入指纹数据，以及激活以便建立与主计算机的通信的输入 - 输出接口电路。在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。

75. 发明授权

US07620769B2 Recycling partially-stale flash blocks using a sliding window for multi-level-cell (MLC) flash memory 失效
标题翻译：使用多层单元（MLC）闪存的滑动窗口回收部分陈旧的闪存块
公开(公告)号：US07620769B2
公开(公告)日：2009-11-17
申请号：US11674645
申请日：2007-02-13
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： H01R13/629 , G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/1044 , G06F2212/7201 , G06F2212/7205 , G06F2212/7209 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.
摘要翻译：闪存块的滑动窗口用于减少闪存中过时数据占用的浪费空间。滑动窗口向下滑过几个闪光块。检查最旧的块是否有效的数据页面，有效的页面被复制到滑动窗口的末尾，以便第一个块只有过时的页面。然后可以擦除第一个块并最终重新使用。 RAM使用表包含滑动窗口中每个块中页面的有效位。当数据写入页面时，页面的有效位从擦除的未写入状态更改为有效状态。之后，当新的主机数据替换该数据时，旧页面的有效位被设置为陈旧状态。 RAM陈旧标记表可以跟踪页面中已经有过时的页面。

76. 发明申请

US20090240873A1 Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System 有权
标题翻译：闪存系统的多级条带和截断信道均衡
公开(公告)号：US20090240873A1
公开(公告)日：2009-09-24
申请号：US12475457
申请日：2009-05-29
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
IPC分类号： G06F12/00 , G06F12/02 , H03M13/00
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0631 , G06F3/0688 , G06F2212/7203 , G06F2212/7208 , G11C11/5678 , G11C13/0004 , G11C29/765
摘要： Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.
摘要翻译：截断将所有闪存通道的可用条带数据容量减小到最小闪存通道的容量。固态磁盘（SSD）具有智能存储交换机，通过截断来保护从条带数据容量中移除的闪存存储。超出条带数据容量的额外存储被访问为不带条纹的分散数据。随着更多的坏块出现，条带数据容量的大小随着时间的推移而减少。一级条形图存储所有闪存通道的条纹和分散容量，并映射散射和条纹数据。每个闪存通道都具有一个非易失性存储器件（NVMD），该器件具有将逻辑块地址（LBA）转换为访问NVMD中闪存的物理块地址（PBA）的低级别控制器。磨损平整和坏块重映射由每个NVMD进行。源和阴影闪存块由NVMD回收。两级智能存储交换机支持三级控制器。

77. 发明申请

US20090113121A1 Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes 有权
标题翻译：具有用于组合Flash写入的命令队列的闪存系统中可部署的部分映射表集
公开(公告)号：US20090113121A1
公开(公告)日：2009-04-30
申请号：US12347306
申请日：2008-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G11C16/102 , G11C2216/30
摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.
摘要翻译：闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。映射所需的RAM大大降低。数据缓冲器存储一页主机写入数据。扇区写入使用数据缓冲区进行合并。当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个映射表。

78. 发明申请

US20080071973A1 ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS 审中-公开
公开(公告)号：US20080071973A1
公开(公告)日：2008-03-20
申请号：US11864671
申请日：2007-09-28
申请人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/7202 , G06F2212/7208 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

79. 发明授权

US08200862B2 Low-power USB flash card reader using bulk-pipe streaming with UAS command re-ordering and channel separation 失效
标题翻译：低功耗USB闪存卡阅读器，采用UAS命令重新排序和通道分离的大容量流式传输
公开(公告)号：US08200862B2
公开(公告)日：2012-06-12
申请号：US12887477
申请日：2010-09-21
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F13/12 , G06F13/00 , G06F12/02
CPC分类号： G06F13/28 , G11C13/0004 , G11C16/102 , G11C2216/30 , Y02D10/14
摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.
摘要翻译：闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。

80. 发明授权

US08108590B2 Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear 失效
标题翻译：多操作写入聚合器使用大量闪存存储器的多个通道中的每个通道中的页面缓冲区和划痕闪存块来减少块磨损
公开(公告)号：US08108590B2
公开(公告)日：2012-01-31
申请号：US12139842
申请日：2008-06-16
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F21/32 , G06F21/78 , G06F2212/1036 , G06F2212/7202 , G06F2212/7208 , G06K19/07 , G06K19/07354
摘要： A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.
摘要翻译：闪存系统具有可以并行访问的多个闪存芯片的通道。主机数据被多通道控制器处理器分配给一个通道，并且累积在多通道页缓冲器中。当到达页面缓冲区中的页面边界时，如果逻辑扇区地址（LSA）匹配，则页缓冲区将被写入目标物理块（如果已满）或与聚合闪存块（AFB）中的旧数据片段组合。因此，使用AFB聚集小片段，减少闪存块的擦除和磨损。发生STOP命令时，页面缓冲区被复制到AFB。每个通道都有一个或多个AFB，它们由AFB跟踪表进行跟踪。

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