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71. 发明授权

US07224021B2 MOSFET with high angle sidewall gate and contacts for reduced miller capacitance 有权
标题翻译：具有高角度侧壁栅极的MOSFET和用于降低铣刀电容的触点
公开(公告)号：US07224021B2
公开(公告)日：2007-05-29
申请号：US11162424
申请日：2005-09-09
申请人： Dureseti Chidambarrao , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Huilong Zhu
发明人： Dureseti Chidambarrao , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7836 , H01L21/26586 , H01L21/28518 , H01L21/76804 , H01L29/1083 , H01L29/665 , H01L29/6659
摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.
摘要翻译：本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面区。与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

72. 发明申请

US20070108531A1 ROTATIONAL SHEAR STRESS FOR CHARGE CARRIER MOBILITY MODIFICATION 有权
标题翻译：充电移动机动车修改的旋转剪应力
公开(公告)号：US20070108531A1
公开(公告)日：2007-05-17
申请号：US11164179
申请日：2005-11-14
申请人： Dureseti Chidambarrao
发明人： Dureseti Chidambarrao
IPC分类号： H01L29/76
CPC分类号： H01L21/76229 , H01L29/517 , H01L29/665 , H01L29/66575 , H01L29/7833 , H01L29/7846
摘要： A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.
摘要翻译：半导体结构及其制造方法利用具有由隔离沟槽包围的有源区域台面的半导体衬底。具有第一应力的第一隔离区域位于隔离沟槽中。具有不同于第一应力的第二应力的第二隔离区也位于隔离沟槽中。第一隔离区域和第二隔离区域的尺寸和尺寸被设置成对活性区域台面进行旋转剪切应力。

73. 发明申请

US20070096215A1 TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENTS 失效
标题翻译：具有介质压力元件的晶体管
公开(公告)号：US20070096215A1
公开(公告)日：2007-05-03
申请号：US11163683
申请日：2005-10-27
申请人： Dureseti Chidambarrao , Brian Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian Greene , Kern Rim
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823412 , H01L29/0653 , H01L29/7846
摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.
摘要翻译：提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。具有水平延伸的上表面的介电应激元件在有源半导体区域的一部分的下方延伸。电介质应力元件与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。在特定结构中，在FET的纵向和/或横向方向上彼此相对的位置处提供两个或更多个介电应激元件。

74. 发明申请

US20070096206A1 GATE ELECTRODE STRESS CONTROL FOR FINFET PERFORMANCE ENHANCEMENT 有权
标题翻译：用于FINFET性能增强的门电极应力控制
公开(公告)号：US20070096206A1
公开(公告)日：2007-05-03
申请号：US11163908
申请日：2005-11-03
申请人： Dureseti Chidambarrao
发明人： Dureseti Chidambarrao
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.
摘要翻译： finFET及其制造方法包括形成在半导体鳍片的沟道区域上的栅电极。半导体鳍具有晶体取向和轴向特定的压阻系数。形成栅电极，该固有应力确定为影响并优选地优化沟道区内的载流子迁移率。为此，固有应力优选地在栅极电极和半导体鳍片沟道区域内提供与轴向特定的压阻系数相匹配的感应的轴向应力。

75. 发明授权

US07198995B2 Strained finFETs and method of manufacture 有权
标题翻译：应变finFET和制造方法
公开(公告)号：US07198995B2
公开(公告)日：2007-04-03
申请号：US10733378
申请日：2003-12-12
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。在具有硬掩模的finFET的侧壁上生长Si外延层，现在是处于张力下的封盖层，防止nFET鳍的横向屈曲。

76. 发明申请

US20070069300A1 PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN 审中-公开
标题翻译：具有嵌入式源/漏极的平面超薄半导体绝缘体通道MOSFET
公开(公告)号：US20070069300A1
公开(公告)日：2007-03-29
申请号：US11162959
申请日：2005-09-29
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/2652 , H01L21/02203 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

77. 发明申请

US20070045775A1 Mobility enhancement in SiGe heterojunction bipolar transistors 失效
标题翻译： SiGe异质结双极晶体管中的迁移增强
公开(公告)号：US20070045775A1
公开(公告)日：2007-03-01
申请号：US11212187
申请日：2005-08-26
申请人： Thomas Adam , Dureseti Chidambarrao
发明人： Thomas Adam , Dureseti Chidambarrao
IPC分类号： H01L29/00
CPC分类号： H01L29/7378 , H01L29/161 , H01L29/165
摘要： The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content. The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.
摘要翻译：本发明涉及在其中具有含SiGe的层的基极区域的高性能异质结双极晶体管（HBT）。含SiGe的层的厚度不超过约100nm，具有预定的临界锗含量。含SiGe的层还具有不小于预定临界锗含量的约80％的平均锗含量。本发明还涉及通过均匀地提高基底层中的锗含量，使其中的平均锗含量不低于临界锗含量的80％，来提高具有含SiGe的基底层的HBT中的载流子迁移率的方法，其基于基底层的厚度计算，条件是基底层不大于100nm厚。

78. 发明申请

US20060273841A1 PROGRAMMING AND DETERMINING STATE OF ELECTRICAL FUSE USING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES 失效
标题翻译：使用具有多个导通状态的场效应晶体管编程和确定电子熔丝状态
公开(公告)号：US20060273841A1
公开(公告)日：2006-12-07
申请号：US11160056
申请日：2005-06-07
申请人： David Hanson , Dureseti Chidambarrao , Gregory Fredeman , David Onsongo
发明人： David Hanson , Dureseti Chidambarrao , Gregory Fredeman , David Onsongo
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or “low” conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.
摘要翻译：提供了一种电路，其可操作以将电可更改元件（例如，熔丝或反熔丝）编程到编程状态，并确定电可更改元件是否处于编程状态。这种电路包括多导通状态场效应晶体管（“多状态FET”），其具有耦合到可电可变元件的源极或漏极中的至少一个，以将电流施加到电可更改元件。多状态FET具有第一阈值电压和第二阈值电压，两者均同时有效，第二阈值电压高于第一阈值电压。栅极可操作以控制多状态FET的操作，包括a）基本上非导通状态; b）当栅极 - 源极电压超过第一阈值电压时，第一或“低”导通状态，其中多态FET被偏置以传导相对低的幅度电流以确定保险丝的状态; 以及c）当所述栅极 - 源极电压超过所述第二阈值电压时，所述第二导电状态是所述多态FET被偏置以导通相对高的编程电流。

79. 发明授权

US07102914B2 Gate controlled floating well vertical MOSFET 失效
标题翻译：门控浮动阱垂直MOSFET
公开(公告)号：US07102914B2
公开(公告)日：2006-09-05
申请号：US10708381
申请日：2004-02-27
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管能够在通常施加到存储和控制单元的两个栅极的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

80. 发明申请

US20060145274A1 NFETs using gate induced stress modulation 审中-公开
公开(公告)号：US20060145274A1
公开(公告)日：2006-07-06
申请号：US11365502
申请日：2006-03-02
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L29/94
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828
摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

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