专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07358104B2 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion 有权
标题翻译：半导体器件的接触部分和包括该接触部分的显示器件的薄膜晶体管阵列面板
公开(公告)号：US07358104B2
公开(公告)日：2008-04-15
申请号：US11359138
申请日：2006-02-22
申请人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
发明人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L21/00
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/124 , H01L27/1244 , H01L27/1248 , H01L27/1288
摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

72. 发明申请

US20080081534A1 METHOD FOR FORMING METAL LINE AND METHOD FOR MANUFACTURING DISPLAY SUBSTRATE BY USING THE SAME 有权
标题翻译：用于形成金属线的方法和使用该方法制造显示衬底的方法
公开(公告)号：US20080081534A1
公开(公告)日：2008-04-03
申请号：US11862837
申请日：2007-09-27
申请人： Min-Seok Oh , Sang-Gab Kim , Shin-Il Choi , Hong-Kee Chin , Yu-Gwang Jeong , Seung-Ha Choi
发明人： Min-Seok Oh , Sang-Gab Kim , Shin-Il Choi , Hong-Kee Chin , Yu-Gwang Jeong , Seung-Ha Choi
IPC分类号： H01J9/12
CPC分类号： H01L21/32136 , G02F1/13439 , G02F2001/136295 , H01L21/02071 , H01L23/53223 , H01L27/124 , H01L29/458 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： In a method for forming a metal line, a first metal layer and a second metal layer are deposited on a substrate. The first metal layer includes aluminum, and the second metal layer includes molybdenum. A photoresist pattern having a line-shape is formed on the second metal layer. The second metal layer is etched with a chlorine-containing etching gas using the photoresist pattern as a mask. The first metal layer is then etched with a mixture of a chlorine-containing gas and nitrogen gas and/or a mixture of a chlorine-containing gas and argon gas as an etching gas. Impurities such as chlorine ions are removed from the base substrate after etching the first metal layer with a fluorine-containing gas, hydrogen gas, or water vapor. A method for manufacturing a display substrate is disclosed using the method for forming a metal line to form source, drain, and gate electrodes and gate lines.
摘要翻译：在金属线的形成方法中，在基板上沉积第一金属层和第二金属层。第一金属层包括铝，第二金属层包括钼。在第二金属层上形成具有线状的光致抗蚀剂图案。使用光致抗蚀剂图案作为掩模，用含氯蚀刻气体蚀刻第二金属层。然后用含氯气体和氮气和/或含氯气体和氩气的混合物的混合物蚀刻第一金属层作为蚀刻气体。在用含氟气体，氢气或水蒸气蚀刻第一金属层之后，从基底衬底去除诸如氯离子的杂质。公开了一种用于形成金属线以形成源极，漏极和栅电极和栅极线的方法，用于制造显示基板的方法。

73. 发明申请

US20060138424A1 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion 有权
标题翻译：半导体器件的接触部分和包括该接触部分的显示器件的薄膜晶体管阵列面板
公开(公告)号：US20060138424A1
公开(公告)日：2006-06-29
申请号：US11359138
申请日：2006-02-22
申请人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
发明人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/124 , H01L27/1244 , H01L27/1248 , H01L27/1288
摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

74. 发明申请

US20060118786A1 Thin film transistor, method of manufacturing the same, display apparatus having the same and method of manufacturing the display apparatus 有权
公开(公告)号：US20060118786A1
公开(公告)日：2006-06-08
申请号：US11232306
申请日：2005-09-20
申请人： Sang-Gab Kim , Shi--Yul Kim , Hong-Sick Park , Hee-Hwan Choe , Hong-Kee Chin , Min-Seok Oh
发明人： Sang-Gab Kim , Shi--Yul Kim , Hong-Sick Park , Hee-Hwan Choe , Hong-Kee Chin , Min-Seok Oh
IPC分类号： H01L29/04
CPC分类号： H01L29/66765 , G02F1/1368 , H01L27/12 , H01L27/124 , H01L29/458
摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

75. 发明授权

US07005670B2 Thin film transistor array substrate for liquid crystal display and method of fabricating the same 失效
标题翻译：用于液晶显示器的薄膜晶体管阵列基板及其制造方法
公开(公告)号：US07005670B2
公开(公告)日：2006-02-28
申请号：US11167155
申请日：2005-06-28
申请人： Sang-Gab Kim , Mun-Pyo Hong
发明人： Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L29/06 , H01L27/01
CPC分类号： H01L29/66765 , G02F2001/13629 , H01L27/124 , H01L29/456 , H01L29/4908
摘要： In a method of fabricating a thin film transistor array substrate, an aluminum-based conductive layer is deposited onto an insulating substrate, and patterned to form a gate line assembly. The gate line assembly includes gate lines, gate electrodes, and gate pads. A gate insulating layer is formed on the substrate with the gate line assembly. A semiconductor layer, and an ohmic contact layer are sequentially formed on the gate insulating layer. A double-layered conductive film with a chrome-based under-layer and an aluminum-based over-layer is deposited onto the substrate, and patterned to form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. The chrome-based under-layer of the conductive film is patterned through dry etching while using Cl2 or HCl as the dry etching gas. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. Indium zinc oxide is deposited onto the substrate, and patterned to thereby form pixel electrodes connected to the drain electrodes through the corresponding contact holes, and subsidiary gate and data pads connected to the gate and data pads through the corresponding contact holes.
摘要翻译：在制造薄膜晶体管阵列基板的方法中，将铝基导电层沉积到绝缘基板上，并被图案化以形成栅极线组件。栅极线组件包括栅极线，栅电极和栅极焊盘。在栅极线组件的基板上形成栅极绝缘层。半导体层和欧姆接触层依次形成在栅绝缘层上。将具有铬基底层和铝基超层的双层导电膜沉积到衬底上，并被图案化以形成数据线组件。数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。通过干蚀刻将导电膜的铬基底层图案化，同时使用Cl 2/2或HCl作为干蚀刻气体。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。将铟锌氧化物沉积在衬底上，并被图案化，从而通过相应的接触孔形成连接到漏电极的像素电极，以及通过对应的接触孔连接到栅极和数据焊盘的辅助栅极和数据焊盘。

76. 发明授权

US06943367B2 Thin film transistor array panel 失效
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US06943367B2
公开(公告)日：2005-09-13
申请号：US10395233
申请日：2003-03-25
申请人： Sang-Gab Kim , Mun-Pyo Hong
发明人： Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： G02F1/1368 , G02F1/136 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/768 , H01L21/77 , H01L21/84 , H01L23/52 , H01L27/12 , H01L29/45 , H01L29/49 , H01L29/786 , H01L29/06 , H01L27/01
CPC分类号： H01L29/66765 , G02F2001/13629 , H01L27/124 , H01L29/456 , H01L29/4908
摘要： In a method of fabricating a thin film transistor array substrate, an aluminum-based conductive layer is deposited onto an insulating substrate, and patterned to form a gate line assembly. The gate line assembly includes gate lines, gate electrodes, and gate pads. A gate insulating layer is formed on the substrate with the gate line assembly. A semiconductor layer, and an ohmic contact layer are sequentially formed on the gate insulating layer. A double-layered conductive film with a chrome-based under-layer and an aluminum-based over-layer is deposited onto the substrate, and patterned to form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. The chrome-based under-layer of the conductive film is patterned through dry etching while using Cl2 or HCl as the dry etching gas. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. Indium zinc oxide is deposited onto the substrate, and patterned to thereby form pixel electrodes connected to the drain electrodes through the corresponding contact holes, and subsidiary gate and data pads connected to the gate and data pads through the corresponding contact holes.
摘要翻译：在制造薄膜晶体管阵列基板的方法中，将铝基导电层沉积到绝缘基板上，并被图案化以形成栅极线组件。栅极线组件包括栅极线，栅电极和栅极焊盘。在栅极线组件的基板上形成栅极绝缘层。半导体层和欧姆接触层依次形成在栅绝缘层上。将具有铬基底层和铝基超层的双层导电膜沉积到衬底上，并被图案化以形成数据线组件。数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。通过干蚀刻将导电膜的铬基底层图案化，同时使用Cl 2/2或HCl作为干蚀刻气体。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。将铟锌氧化物沉积在衬底上，并被图案化，从而通过相应的接触孔形成连接到漏电极的像素电极，以及通过对应的接触孔连接到栅极和数据焊盘的辅助栅极和数据焊盘。

77. 发明授权

US08305507B2 Thin film transistor array panel having improved storage capacitance and manufacturing method thereof 有权
标题翻译：具有改善的存储电容的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08305507B2
公开(公告)日：2012-11-06
申请号：US11356853
申请日：2006-02-17
申请人： Hye-Young Ryu , Jang-Soo Kim , Sang-Gab Kim , Hong-Kee Chin , Min-Seok Oh , Hee-Hwan Choe , Shi-Yul Kim
发明人： Hye-Young Ryu , Jang-Soo Kim , Sang-Gab Kim , Hong-Kee Chin , Min-Seok Oh , Hee-Hwan Choe , Shi-Yul Kim
IPC分类号： G02F1/1343
CPC分类号： G02F1/136286 , G02F1/133345 , G02F1/1362 , G02F2001/136222 , G02F2202/02
摘要： A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括栅极线，与栅极线相交的数据线，与栅极和数据线分开的存储电极，连接到栅极和数据线并具有漏极的薄膜晶体管连接到漏电极的像素电极，薄膜晶体管上的第一绝缘层，并且设置在像素电极下方;第二绝缘层，设置在第一绝缘层上，并且具有使存储电极上的第一绝缘层露出的开口。

78. 发明授权

US08173493B2 Thin film transistor array panel and fabrication 有权
标题翻译：薄膜晶体管阵列和制造
公开(公告)号：US08173493B2
公开(公告)日：2012-05-08
申请号：US12765698
申请日：2010-04-22
申请人： Sang-Gab Kim , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
发明人： Sang-Gab Kim , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/124 , G02F2001/13629 , H01L29/458
摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.
摘要翻译：本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

79. 发明授权

US08093595B2 Thin film array panel and manufacturing method thereof 有权
标题翻译：薄膜阵列面板及其制造方法
公开(公告)号：US08093595B2
公开(公告)日：2012-01-10
申请号：US12609568
申请日：2009-10-30
申请人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
发明人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
IPC分类号： H01L29/04
CPC分类号： H01L27/1259 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L27/1214 , H01L27/124 , H01L27/1288 , H01L27/3262
摘要： A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer, forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.
摘要翻译：提供一种制造薄膜阵列面板的方法，其包括：形成在基底上的栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在所述半导体层上形成欧姆接触层; 形成至少设置在所述欧姆接触层上的数据线和漏电极，在所述数据线上形成氧化物; 使用数据线和漏电极作为蚀刻掩模蚀刻欧姆接触层; 以及形成连接到所述漏电极的像素电极。

80. 发明授权

US08017459B2 Method of fabricating a thin film transistor array substrate 有权
标题翻译：制造薄膜晶体管阵列基板的方法
公开(公告)号：US08017459B2
公开(公告)日：2011-09-13
申请号：US12484116
申请日：2009-06-12
申请人： Dong-Ju Yang , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
发明人： Dong-Ju Yang , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Jung-Suk Bang
IPC分类号： H01L21/00
CPC分类号： H01L27/1248 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/7869
摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.
摘要翻译：提出了制造薄膜晶体管阵列基板的方法。该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到作为数据互连线的延伸线的漏电极。在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。形成连接到漏电极的像素电极。两个钝化层具有相同的组成，但是在不同的温度下进行处理。还提出了以上述方式制备的薄膜晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式