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71. 发明授权

US06700161B2 Variable resistor structure and method for forming and programming a variable resistor for electronic circuits 失效
标题翻译：用于形成和编程用于电子电路的可变电阻器的可变电阻器结构和方法
公开(公告)号：US06700161B2
公开(公告)日：2004-03-02
申请号：US10146072
申请日：2002-05-16
申请人： Louis Lu-Chen Hsu , Chandrasekhar Narayan , Carl J. Radens
发明人： Louis Lu-Chen Hsu , Chandrasekhar Narayan , Carl J. Radens
IPC分类号： H01L2973
CPC分类号： H01L23/5254 , H01L23/5252 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value by heating the programmable element by either providing a current flow through the programmable element, or directing a laser beam onto the programmable element. The conductive materials are interdiffused to form an alloy of the conductive materials. A resistance value of the variable resistor is determined, at least in part, by the degree to which the conductive materials are alloyed or interdiffused. The method and structure of the variable resistor prevents ablative damage to adjoining circuit structure, allowing tighter pitch, and has application to digital programmable elements, and to resistance trimming for impedance matching in RF integrated circuits.
摘要翻译：用于形成可变电阻器的非烧蚀结构和方法包括提供包括两个或多个不同导电材料的可编程电阻元件，并且通过加热可编程元件来提供可编程电阻元件的电流来改变可编程电阻元件的有限值，通过可编程元件，或将激光束引导到可编程元件上。导电材料相互扩散以形成导电材料的合金。可变电阻器的电阻值至少部分地由导电材料合金化或相互扩散的程度决定。可变电阻器的方法和结构防止邻接电路结构的烧蚀损坏，使得更紧密的间距，并且应用于数字可编程元件，以及用于RF集成电路中的阻抗匹配的电阻调整。

72. 发明授权

US06632741B1 Self-trimming method on looped patterns 失效
标题翻译：循环模式自修整方法
公开(公告)号：US06632741B1
公开(公告)日：2003-10-14
申请号：US09619664
申请日：2000-07-19
申请人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl J. Radens
发明人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21302
CPC分类号： H01L21/0334
摘要： A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material along the sidewalls of the features in the first material.
摘要翻译：一种自修剪图案的方法包括在沉积在基底上的第一材料中形成包含多个规则或不规则特征的图案，沉积第二材料的共形层，并蚀刻第二材料以形成第二材料的间隔物第一种材料的特征侧壁。

73. 发明授权

US06570207B2 Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex 失效
标题翻译：在使用垂直阵列器件单元复合体的DRAM工艺中创建垂直电容器和反熔丝的结构和方法
公开(公告)号：US06570207B2
公开(公告)日：2003-05-27
申请号：US09736496
申请日：2000-12-13
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L23/5252 , H01L27/10841 , H01L27/10864 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.
摘要翻译：提供一种集成电路芯片，其具有常规DRAM垂直传送装置和可以直接访问的集成垂直存储电容器或反熔丝，而不必打开传输门。直接访问集成电容器或反熔丝的机构可以是垂直单元内的修改的掺杂分布，其提供低电阻穿通FET。或者，机构可以是垂直单元内的一对重叠或几乎重叠的扩散。

74. 发明授权

US06538295B1 Salicide device with borderless contact 有权
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06538295B1
公开(公告)日：2003-03-25
申请号：US09645499
申请日：2000-08-25
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

75. 发明授权

US06518119B2 Strap with intrinsically conductive barrier 失效
标题翻译：带本征导电屏障
公开(公告)号：US06518119B2
公开(公告)日：2003-02-11
申请号：US09886065
申请日：2001-06-21
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L29/945
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

76. 发明授权

US06396096B1 Design layout for a dense memory cell structure 有权
标题翻译：密集存储单元结构的设计布局
公开(公告)号：US06396096B1
公开(公告)日：2002-05-28
申请号：US09597401
申请日：2000-06-21
申请人： Young-Jin Park , Carl J. Radens
发明人： Young-Jin Park , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L27/10808 , H01L27/10891 , Y10S257/908 , Y10S257/909
摘要： A design layout for a memory cell structure is provided that achieves maximized channel length on the active areas, while not constricting the contact area of the capacitor contacts is provided. Specifically, the layout design provides a semiconductor memory structure that includes wordlines, bitlines, and sub-8F2 memory cells in a semiconductor substrate, said memory cells comprising a transfer gate transistor having a source region and a drain region formed in said substrate and a gate electrode, a memory cell stacked storage capacitor, a wordline conductor portion contacting said gate electrode, said wordline gate conductor portion forming part of one of said wordlines, a bitline contact to said source region, said bitline contact connecting said source region to one of said bitlines, and a capacitor contact between said capacitor and said drain region, wherein for at least one of said cells, said bitline contact and said capacitor contact are positioned at a distance from each other greater than from said bitline contact to a closest contact of another of said cells and greater than from said capacitor contact to a closest contact of another of said cells.
摘要翻译：提供了一种用于存储单元结构的设计布局，其在有源区域上实现最大化的通道长度，同时不限制电容器触点的接触面积。具体来说，布局设计提供半导体存储器结构，其包括半导体衬底中的字线，位线和子-8F2存储器单元，所述存储单元包括具有形成在所述衬底中的源极区和漏极区的转移栅极晶体管和栅极存储单元堆叠存储电容器，与所述栅电极接触的字线导体部分，形成所述字线之一的所述字线栅极导体部分，与所述源极区域的位线接触，所述位线接触件将所述源极区域连接到所述位线和所述电容器与所述漏极区域之间的电容器接触，其中对于所述单元中的至少一个，所述位线接触和所述电容器触点彼此间隔一定距离大于从所述位线接触到另一个的最接近的接触并且大于从所述电容器接触到另一个所述电池的最接近的接触。

77. 发明授权

US06380027B2 Dual tox trench dram structures and process using V-groove 失效
标题翻译：双毒tox沟结构和工艺采用V型槽
公开(公告)号：US06380027B2
公开(公告)日：2002-04-30
申请号：US09225127
申请日：1999-01-04
申请人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
发明人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
IPC分类号： H01L21242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10894
摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
摘要翻译：用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及其中所述第一氧化物比所述第二氧化物厚。

78. 发明授权

US06320215B1 Crystal-axis-aligned vertical side wall device 有权
标题翻译：水晶轴对齐垂直侧壁装置
公开(公告)号：US06320215B1
公开(公告)日：2001-11-20
申请号：US09359292
申请日：1999-07-22
申请人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译：一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件在侧壁上的刻面晶体区域上。小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

79. 发明授权

US06268638B1 Metal wire fuse structure with cavity 失效
标题翻译：金属线熔丝结构带腔
公开(公告)号：US06268638B1
公开(公告)日：2001-07-31
申请号：US09258563
申请日：1999-02-26
申请人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
发明人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
IPC分类号： H01L2702
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
摘要翻译：集成电路具有初级器件，并且冗余器件通过至少一个熔丝被选择性地代替初级器件。熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。

80. 发明授权

US06174762B1 Salicide device with borderless contact 失效
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06174762B1
公开(公告)日：2001-01-16
申请号：US09260311
申请日：1999-03-02
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L218234
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

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