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71. 发明授权

US5777946A Semiconductor memory circuit equipped with a column addressing circuit having a shift register 失效
标题翻译：配备有具有移位寄存器的列寻址电路的半导体存储器电路
公开(公告)号：US5777946A
公开(公告)日：1998-07-07
申请号：US770404
申请日：1996-12-20
申请人： Kazuko Inuzuka , Shigeo Ohshima , Katsushi Nagaba
发明人： Kazuko Inuzuka , Shigeo Ohshima , Katsushi Nagaba
IPC分类号： G11C11/407 , G11C8/04 , G11C11/408
CPC分类号： G11C8/04
摘要： The present invention provides a semiconductor memory circuit capable of high-speed access to a predetermined column portion by a simplified high-speed addressing circuit. The memory circuit in a DRAM is such that a portion of a column addressing circuit normally comprising a counter constitutes a shift register in a column addressing circuit at a preceding stage of a column address buffer so that a plurality of address signal wrappings are realized for accessing the predetermined column portion.
摘要翻译：本发明提供一种能够通过简化的高速寻址电路高速访问预定列部分的半导体存储器电路。 DRAM中的存储器电路使得通常包括计数器的列寻址电路的一部分在列地址缓冲器的前级构成列寻址电路中的移位寄存器，从而实现多个地址信号包装以进行访问预定列部分。

72. 发明授权

US5703381A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5703381A
公开(公告)日：1997-12-30
申请号：US557731
申请日：1995-11-13
申请人： Kiyoaki Iwasa , Shigeo Ohshima
发明人： Kiyoaki Iwasa , Shigeo Ohshima
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , H01L21/822 , H01L23/544 , H01L27/04 , H01L23/58
CPC分类号： H01L22/34 , G01R31/2884
摘要： A semiconductor integrated circuit includes a rectangular semiconductor chip having a main surface, a plurality of pads formed in a peripheral portion of the main surface of the semiconductor chip, for connection to external connecting members, a plurality of circuit elements of an integrated circuit formed in an area of the main surface other than an area in which the plurality of pads are formed, and at least one characteristic evaluating circuit element connected to at least one of the plurality of circuit elements of the integrated circuit by sharing an impurity doped region which forms part of the at least one circuit element with the at least one circuit element of the integrated circuit in an area of the main surface other than the peripheral portion in which the plurality of pads are formed.
摘要翻译：半导体集成电路包括具有主表面的矩形半导体芯片，形成在半导体芯片的主表面的周边部分中的多个焊盘，用于连接到外部连接构件，多个集成电路的电路元件形成在除了形成多个焊盘的区域之外的主表面的区域，以及至少一个特征评估电路元件，其通过共享形成的杂质掺杂区域而与集成电路的多个电路元件中的至少一个连接所述至少一个电路元件的一部分与所述集成电路的所述至少一个电路元件在所述主表面的除了形成所述多个焊盘的外围部分之外的区域中。

73. 发明授权

US5287306A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5287306A
公开(公告)日：1994-02-15
申请号：US718449
申请日：1991-06-20
申请人： Shinji Miyamoto , Shigeo Ohshima
发明人： Shinji Miyamoto , Shigeo Ohshima
IPC分类号： G11C11/413 , G11C5/14 , G11C7/10 , G11C11/407 , G11C11/409 , G11C11/417 , H03K17/16 , H03K17/687 , H03K19/0175 , G11C7/00
CPC分类号： G11C5/14 , G11C7/1051
摘要： A semiconductor memory device includes a first power source having a non-ground potential V.sub.cc1 terminal and a ground potential V.sub.ss1 terminal. The internal circuit is supplied with power from the first power source. The first power source is dedicated to the internal circuit. The internal circuit selects a memory cell of a memory cell array in accordance with an inputted address. The internal circuit has a first output terminal and a second output terminal the first output terminal outputs one of a pair of potential V.sub.cc1 and V.sub.ss1 and the second output terminal outputs the other of the pair in accordance with the data in the selected memory cell. A second power source has a non-ground potential V.sub.cc2 terminal and a ground potential V.sub.ss2 terminal. The output circuit is supplied with power from the second power source which is dedicated to the output circuit. The output circuit has first and second transistors serially connected between the V.sub.cc2 terminal and V.sub.ss2. The control terminals of the first and second transistors are connected to the first and second output terminals. A third transistor is connected between an interconnection between the first and second transistors connected to a data output from which data is externally outputted and the first output terminal, and the control terminal of the third transistor being connected to the second output terminal.
摘要翻译：半导体存储器件包括具有非接地电位Vcc1端子和接地电位Vss1端子的第一电源。内部电路由第一个电源供电。第一个电源专用于内部电路。内部电路根据输入的地址选择存储单元阵列的存储单元。内部电路具有第一输出端子和第二输出端子，第一输出端子输出一对电位Vcc1和Vss1中的一个，第二输出端子根据所选存储单元中的数据输出该对中的另一个。第二电源具有非接地电位Vcc2端子和接地电位Vss2端子。输出电路由专用于输出电路的第二电源供电。输出电路具有串联连接在Vcc2端子和Vss2之间的第一和第二晶体管。第一和第二晶体管的控制端子连接到第一和第二输出端子。第三晶体管连接在与外部输出数据的数据输出端连接的第一和第二晶体管之间的互连和第一输出端子之间，第三晶体管的控制端子连接到第二输出端子。

74. 发明授权

US5251180A Semiconductor memory device 失效
公开(公告)号：US5251180A
公开(公告)日：1993-10-05
申请号：US799988
申请日：1991-11-29
申请人： Shigeo Ohshima
发明人： Shigeo Ohshima
IPC分类号： G11C8/18 , G11C11/4076 , G11C11/407
CPC分类号： G11C11/4076 , G11C8/18 , G11C2207/061
摘要： In the semiconductor memory composed of divided dynamic memory cell arrays, when a drive signal is supplied to a word line selected by a row decoder, data stored at the memory cells connected to the word line are transferred to bit lines, respectively. A change in potential at the bit line pair is amplified by the sense amplifier to completely read the data. To prevent the bit line pairs from being sensed erroneously due to fluctuation of the timings at which the word line driving signals are generated in the divided cell arrays, a bit line sense signal is generated a predetermined delay time after all the word line driving signals have been generated, in order to drive all the sense amplifiers simultaneously, so that data can be definitely read from the memory cells to the bit lines. To detect that all the word line driving signals have been generated, a drive signal detection section is connected between word line driving circuits for all the divided cell arrays and a delay circuit connected to a sense amplifier driving circuit.

75. 发明授权

US5229971A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5229971A
公开(公告)日：1993-07-20
申请号：US613001
申请日：1990-11-15
申请人： Masakazu Kiryu , Shigeo Ohshima
发明人： Masakazu Kiryu , Shigeo Ohshima
IPC分类号： G11C11/401 , G11C7/00 , G11C11/407 , G11C11/4096
CPC分类号： G11C7/00 , G11C11/4096
摘要： A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, registers and a control unit. The control unit allows the write operational mode of the column decoder to switch. In the ordinary write operational mode, data in the n registers are written into the active memory cells of the n memory cell columns in on column block selected by the column decoder, respectively. In the block write mode, data in the n registers are written into active memory cells of the n memory cell columns in the 2.sup.N column blocks selected by the column decoder, respectively. Another semiconductor memory device comprises N memory units. Each memory unit comprises a memory cell array, a row decoder, a first column decoder, a second column decoder, a data input terminal, registers and a control circuit. The control circuit is operative to allow the operational mode. When the device is in the ordinary mode, data latched in the register is written into one memory cell connected to one word line selected by the row decoder of one column selected by the first column decoder of column blocks selected by the second decoder. While when the device is in the block write mode, data latched in the register is written at the same time into j memory cells connected to one word line selected by the row decoder of column blocks selected by the second column decoder.

76. 发明授权

US4864164A Integrated circuit with switching noise reduction by feedback 失效
标题翻译：通过反馈降低开关噪声的集成电路
公开(公告)号：US4864164A
公开(公告)日：1989-09-05
申请号：US254915
申请日：1988-10-07
申请人： Shigeo Ohshima , Youichi Suzuki , Makoto Segawa
发明人： Shigeo Ohshima , Youichi Suzuki , Makoto Segawa
IPC分类号： G11C11/413 , G11C5/06 , G11C5/14 , G11C7/10 , G11C11/401 , G11C11/409 , H01L27/10 , H03K19/003
CPC分类号： G11C7/1057 , G11C5/063 , G11C5/14 , G11C7/1051 , G11C7/1078 , G11C7/1084 , H03K19/00361
摘要： An integrated circuit includes an input buffer circuit and an output buffer circuit. The source voltage to the input buffer circuit and the output buffer circuit are supplied through bonding pads formed independently on a semiconductor chip, and electrically connected to a source potential lead pin. The input node of the input buffer circuit is coupled to the source potential of the output buffer circuit with a capacitor.

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