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71. 发明申请

US20090212815A1 TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD 失效
标题翻译：三叶式襟翼浮雕系统及方法
公开(公告)号：US20090212815A1
公开(公告)日：2009-08-27
申请号：US12391993
申请日：2009-02-24
申请人： Scott Pitkethly , Robert P. Masleid
发明人： Scott Pitkethly , Robert P. Masleid
IPC分类号： H03K17/16
CPC分类号： H03K3/356191 , H03K3/012 , H03K17/162 , H03K17/6872
摘要： A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.
摘要翻译：公开了三重锁存触发器系统和方法。在一个实施例中，三重锁存触发器系统包括上拉锁存器，下拉锁存器，主锁存器和输出端。上拉闩锁驱动一个上拉节点。下拉锁存器驱动下拉节点。主锁存器记录三重锁存触发器系统的状态。用于根据上拉锁存器，下拉锁存器和主锁存器的输出输出逻辑值的输出。

72. 发明授权

US07336103B1 Stacked inverter delay chain 有权
标题翻译：堆叠变频器延时链
公开(公告)号：US07336103B1
公开(公告)日：2008-02-26
申请号：US10864271
申请日：2004-06-08
申请人： Robert P. Masleid , James B. Burr
发明人： Robert P. Masleid , James B. Burr
IPC分类号： H03K19/094
CPC分类号： H03K5/1252 , H03K5/133 , H03K17/6872 , H03K19/00361
摘要： Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.
摘要翻译：堆叠式逆变器延时链。根据本发明的第一实施例，两个p型器件的串联堆叠耦合到三个n型器件的串联堆叠，形成堆叠的反相器，其包括期望的延迟，管芯面积和功率特性。两个堆叠的反相器耦合在一起以形成堆叠的反相器延迟链，其在与常规逆变器的常规延迟链相比在管芯面积，主动和无源功耗方面更有效。

73. 发明授权

US06864524B2 Hybrid bulk/silicon-on-insulator multiprocessors 失效
标题翻译：混合体/绝缘体上硅多工器
公开(公告)号：US06864524B2
公开(公告)日：2005-03-08
申请号：US10786276
申请日：2004-02-24
申请人： Robert P. Masleid , Gregory S. Scott
发明人： Robert P. Masleid , Gregory S. Scott
IPC分类号： G06F11/20 , G06F12/08 , G06F12/16 , G06F15/16 , H01L21/762 , H01L21/822 , H01L21/84 , H01L27/04 , H01L27/12 , H01L27/108 , H01L29/00
CPC分类号： G06F12/0893 , H01L21/76243 , H01L21/84
摘要： A multiprocessor integrated circuit is disclosed. A preferred embodiment of a multiprocessor chip has microprocessors formed on silicon-on-insulator regions and dynamic random access memory level-2cache memories or level-3 cache memories formed on bulk regions of the chip. A preferred embodiment includes a redundant architecture having a signal bus for coupling the microprocessors to the level-2 or level-3 cache memories in which the signal bus includes a programmable selector circuit for bypassing defective microprocessors or defective level-2 or level-3 cache memories.
摘要翻译：公开了一种多处理器集成电路。多处理器芯片的优选实施例具有形成在绝缘体上硅区域上的微处理器和形成在芯片的体区域上的动态随机存取存储器级别2cache存储器或级3高速缓存存储器。优选实施例包括具有用于将微处理器耦合到二级或三级高速缓冲存储器的信号总线的冗余架构，其中信号总线包括用于绕过有缺陷的微处理器或有缺陷的二级或三级高速缓存的可编程选择器电路回忆

74. 发明授权

US5615160A Minimal recharge overhead circuit for domino SRAM structures 失效
标题翻译：用于多米诺SRAM结构的最小补充开销电路
公开(公告)号：US5615160A
公开(公告)日：1997-03-25
申请号：US525994
申请日：1995-09-08
申请人： Larry B. Phillips , Robert P. Masleid , John S. Muhich
发明人： Larry B. Phillips , Robert P. Masleid , John S. Muhich
IPC分类号： G11C11/417 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/417
摘要： A system and method for improving a domino SRAM that eliminates the need for additional transistors in series with evaluation transistors. The regular structure inherent in RAM arrays is used to minimize both the effective recharge cycle time and the recharge power required to recharge the various levels of domino SRAM circuits. Using a clock signal as a reference, recharge signals are timed to each other and to other functional signals. By adjusting buffers and wiring delays associated with each recharge signal, the recharge signals sent to each level of logic are delayed until the recharge of the previous level is complete.
摘要翻译：用于改进多米诺SRAM的系统和方法，其不需要与评估晶体管串联的附加晶体管。 RAM阵列固有的常规结构用于最大限度地减少有效充电周期时间和为多米诺骨牌SRAM电路充电所需的充电功率。使用时钟信号作为参考，再充电信号相互定时和其他功能信号。通过调整与每个充电信号相关联的缓冲器和接线延迟，发送到每个逻辑电平的充电信号被延迟，直到先前电平的充电完成。

75. 发明授权

US5614845A Independent clock edge regulation 失效
标题翻译：独立的时钟边缘调节
公开(公告)号：US5614845A
公开(公告)日：1997-03-25
申请号：US525997
申请日：1995-09-08
申请人： Robert P. Masleid
发明人： Robert P. Masleid
IPC分类号： H03K5/151 , H03K19/00
CPC分类号： H03K5/151
摘要： A clock regulator that provides two controlled timing references per clock cycle on a single clock distribution. The regulator includes two phase detectors and phase aligner pairs to independently regulate both rising and falling edges of the clock distribution, rather than regulating only one edge as conventional regulators.
摘要翻译：时钟调节器，在单个时钟分配上，每个时钟周期提供两个受控定时参考。调节器包括两个相位检测器和相位对准器对，用于独立调节时钟分配的上升沿和下降沿，而不是仅调节一个边沿作为传统的稳压器。

76. 发明授权

US5442776A Electronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking system 失效
标题翻译：电子调谐计算机时钟系统和电子调谐计算机时钟系统配线的方法
公开(公告)号：US5442776A
公开(公告)日：1995-08-15
申请号：US269226
申请日：1994-06-30
申请人： Robert P. Masleid , Nandor G. Thoma
发明人： Robert P. Masleid , Nandor G. Thoma
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H03K5/15 , G06F15/20 , H03J1/00
CPC分类号： H03K5/1504
摘要： A resonant clocking system is described which utilizes a feedback clock signal from the master clock node on a clocked chip and wherein the feedback clock signal is detected with a phase detector to determine the relevant phasing of the transmitted and the feedback received clock signals. An electronically controllable delay element is disposed within the transmission path of the clock signal on both the transmission leg and the return leg so that equal amounts of delay time may be added to the flight time in each direction. The delay may be electronically controlled to bring a "Transmitted Clock" pulse and a "Received Clock" pulse into phase. By insuring that the delay time for the entire transmission of the circuit by a particular clock pulse is an even number of cycle times, the master clock node on the clocked chip also may be controlled to be in phase with the "Transmitted Clock" pulse signal. This may be accomplished by initially calibrating the system at one-half of normal operating frequency and bringing "Transmitted Clock" pulse and "Received Clock" or feedback pulse into phase. Thereafter, upon returning to normal operating frequency, there always will be an even integral number of cycles of time delay between the transmission of the clock pulse by the oscillator and the receipt of that identical clock pulse by the phase detector; additionally, the pulse at the master clock mode will be in phase.
摘要翻译：描述了谐振时钟系统，其利用来自时钟芯片上的主时钟节点的反馈时钟信号，并且其中用相位检测器检测反馈时钟信号，以确定所发射的反馈和反馈接收的时钟信号的相关定相。电子可控延迟元件设置在传输腿和返回腿上的时钟信号的传输路径内，使得可以在每个方向上将等量的延迟时间添加到飞行时间。延迟可以被电子控制以使“发送时钟”脉冲和“接收时钟”脉冲进入相位。通过确保通过特定时钟脉冲整个电路传输的延迟时间是偶数个周期时间，时钟芯片上的主时钟节点也可以被控制为与“发送时钟”脉冲信号同相。这可以通过在正常工作频率的一半初始校准系统并且将“发送时钟”脉冲和“接收时钟”或反馈脉冲进入相位来实现。此后，在返回到正常工作频率之后，在振荡器发送时钟脉冲和由相位检测器接收到相同的时钟脉冲之间总是有一个偶数个周期的时间延迟; 此外，主时钟模式下的脉冲将同相。

77. 发明授权

US5036215A Pass gate multiplexer receiver circuit 失效
标题翻译：通门复用器接收电路
公开(公告)号：US5036215A
公开(公告)日：1991-07-30
申请号：US471893
申请日：1990-01-29
申请人： Robert P. Masleid , Robert F. Sechler
发明人： Robert P. Masleid , Robert F. Sechler
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/06 , H01L27/088 , H01L27/092 , H01L27/118
CPC分类号： H01L27/0259 , H01L27/092 , H01L27/11898
摘要： A pass gate multiplexer receiver integrated circuit on a semiconductor substrate including a pass gate circuit including first and second field effect transistors of opposite polarity for providing an input signal to an output line, the first transistor including a first bipolar transistor for providing clamping an electrostatic discharge protection and the second transistor including a second bipolar transistor for providing clamping and electrostatic discharge protection. A control circuit is connected to the pass gate to control operation. In a second embodiment the pass gate further includes a clamping circuit to provide further clamping and electrostatic discharge protection.

78. 发明授权

US08946905B2 Via structure for integrated circuits 有权
标题翻译：集成电路通路结构
公开(公告)号：US08946905B2
公开(公告)日：2015-02-03
申请号：US13169255
申请日：2011-06-27
申请人： Robert P. Masleid
发明人： Robert P. Masleid
IPC分类号： H01L23/528 , H01L23/522
CPC分类号： H01L23/5226 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias.
摘要翻译：公开了一种具有堆叠通孔同心布置的集成电路（IC）。该IC包括分别在第一和第二金属层上的第一和第二多条信号线。第二金属层布置在第一金属层和硅层之间。 IC还包括在预定区域中实现的通孔结构，并且通过相应的第一和第二多个通孔将第一和第二多条信号线中的每一条连接到硅层中的电路。第一和第二多个的每个通孔具有沿着垂直轴从其各自的金属层延伸到硅层的中心点。第二多个通孔中的每一个的中心比第一多个通孔中的任一个的相应中心更靠近预定区域的周边。

79. 发明授权

US08289088B2 Inverting difference oscillator 有权
标题翻译：反相差振荡器
公开(公告)号：US08289088B2
公开(公告)日：2012-10-16
申请号：US12495088
申请日：2009-06-30
申请人： Anand Dixit , Robert P. Masleid
发明人： Anand Dixit , Robert P. Masleid
IPC分类号： H03K3/03 , G01R23/175 , G01R31/27
CPC分类号： H03K3/0315 , H03K3/02
摘要： The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.
摘要翻译：所描述的实施例提供可配置的脉冲发生器电路。更具体地，所描述的实施例包括脉冲发生器电路; 反相差分振荡器（IDO）使能电路耦合到脉冲发生器电路; 以及耦合到IDO使能电路的禁用信号。当禁用信号被断言时，禁用IDO使能电路，脉冲发生器电路被配置为脉冲发生器。相反，当禁用信号无效时，启用IDO使能电路，并将脉冲发生器电路配置为IDO的一部分。

80. 发明授权

US08269544B2 Power-supply noise suppression using a frequency-locked loop 有权
标题翻译：使用频率锁定环路进行电源噪声抑制
公开(公告)号：US08269544B2
公开(公告)日：2012-09-18
申请号：US12896650
申请日：2010-10-01
申请人： David J. Greenhill , Robert P. Masleid , Georgios K. Konstadinidis , King C. Yen , Sebastian Turullols
发明人： David J. Greenhill , Robert P. Masleid , Georgios K. Konstadinidis , King C. Yen , Sebastian Turullols
IPC分类号： H03H11/26
CPC分类号： H03L7/18
摘要： An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.
摘要翻译：描述了一种集成电路，其包括基于DCO和关键路径的电源电压的变化来调整集成电路的关键路径的时钟频率的数字控制振荡器（DCO）。该DCO可以包括在包括频率锁定环（FLL）的反馈控制环路中，并且其基于参考频率确定关键路径的平均时钟频率。此外，DCO可以具有可选择的延迟特性，其指定作为电源电压的函数的DCO的延迟灵敏度，从而大致匹配所制造的关键路径的延迟特性。此外，对于具有大于与集成电路的芯片封装相关联的谐振频率的电源电压的变化，时钟频率的调整可以与电源电压和可选延迟特性的变化成比例。

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