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71. 发明授权

US5376566A N-channel field effect transistor having an oblique arsenic implant for lowered series resistance 失效
标题翻译：具有用于降低串联电阻的倾斜砷植入物的N沟道场效应晶体管
公开(公告)号：US5376566A
公开(公告)日：1994-12-27
申请号：US152116
申请日：1993-11-12
申请人： Fernando Gonzalez
发明人： Fernando Gonzalez
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8242 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10873 , H01L21/26586 , H01L29/6659 , H01L29/66659 , H01L27/10888
摘要： An improved N-channel field-effect transistor is fabricated by performing a vertical N- implant, aligned to the vertical edges of the gate electrode, in both the source and drain regions of the device. In a first embodiment of the invention intended for use in dynamic random access memory access devices, a dielectric spacer is then formed on the sidewall of the gate electrode adjacent the drain (i.e., the regions which functions as the bitline contact in a DRAM memory cell). A vertical N+ implant, aligned to the exposed vertical edge of that spacer, is performed, in addition to an oblique implant of an N-type impurity. The oblique implant dosage is significantly greater than the N- implant dosage, but significantly less than the N+ implant dosage. In a second embodiment of the invention intended for use in applications where the transistor has no capacitive storage node, spacers are formed on both sidewalls of the gate electrode and the N+ implant, as well as the oblique N-type implant are performed in both the source and drain regions of the device. In preferred embodiments of the invention, phosphorus is utilized as the N- implant impurity, while arsenic is utilized for the other two N-type implants. The oblique implant provides not only reduced electric field strength in the channel region, but also reduced series resistance.
摘要翻译：通过在器件的源极和漏极区域中执行与栅电极的垂直边缘对准的垂直N-注入来制造改进的N沟道场效应晶体管。在本发明的第一实施例中，旨在用于动态随机存取存储器存取器件中，然后在邻近漏极的栅电极的侧壁上形成电介质间隔物（即，在DRAM存储器单元中用作位线接触的区域）。除了N型杂质的倾斜注入之外，还执行与该间隔物的暴露的垂直边缘对准的垂直N +注入。倾斜植入剂量显着大于N-植入剂量，但显着小于N +植入剂量。在本发明的第二个实施例中，意图用于晶体管没有电容存储节点的应用中，在栅电极和N +注入的两个侧壁上形成间隔物，以及斜面N型注入都在源极和漏极区域。在本发明的优选实施方案中，磷用作N-注入杂质，而砷用于其它两种N型植入物。倾斜植入物不仅在沟道区域中提供了降低的电场强度，而且降低了串联电阻。

72. 发明授权

US5244826A Method of forming an array of finned memory cell capacitors on a semiconductor substrate 失效
标题翻译：在半导体衬底上形成鳍状存储单元电容器阵列的方法
公开(公告)号：US5244826A
公开(公告)日：1993-09-14
申请号：US870606
申请日：1992-04-16
申请人： Fernando Gonzalez , Roger R. Lee
发明人： Fernando Gonzalez , Roger R. Lee
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/87
摘要： An array of finned memory cell capacitors on a semiconductor substrate includes: a) an array of electrically insulated word lines atop a semiconductor substrate; b) first and second active regions adjacent the word lines; c) capacitor storage nodes electrically connecting with the first active regions, individual capacitor storage nodes including: i) a layer of first conductive material conductively connecting with a first active region, the layer of first conductive material having opposed outer lateral edges, and ii) a layer of conductively doped storage node polysilicon overlying and conductively connecting with the layer of first conductive material, the storage node polysilicon projecting laterally outward beyond the outer lateral edges of the first conductive material to define opposing storage node capacitor fins projecting laterally above adjacent word lines; d) a layer of capacitor dielectric electrically connecting with the storage node capacitor fins; e) a layer of electrically conductive cell polysilicon electrically connecting with the capacitor dielectric layer; and f) bit lines electrically connecting with the second active regions. The invention also includes a method of forming memory cell capacitors.
摘要翻译：半导体衬底上的鳍状存储单元电容器阵列包括：a）半导体衬底顶部的电绝缘字线阵列; b）与字线相邻的第一和第二有源区; c）与第一有源区电连接的电容器存储节点，各个电容器存储节点包括：i）与第一有源区导电连接的第一导电材料层，第一导电材料层具有相对的外侧边缘，以及ii）导电掺杂存储节点多晶硅层覆盖并与第一导电材料层导电连接，存储节点多晶硅横向向外突出超出第一导电材料的外侧边缘，以限定在相邻字线之上横向突出的相对的存储节点电容器鳍片 ; d）与存储节点电容器散热片电连接的电容器电介质层; e）与电容器介电层电连接的导电单元多晶硅层; 以及f）与第二有源区域电连接的位线。本发明还包括形成存储单元电容器的方法。

73. 发明授权

US5192703A Method of making tungsten contact core stack capacitor 失效
标题翻译：制造钨接触芯堆叠电容器的方法
公开(公告)号：US5192703A
公开(公告)日：1993-03-09
申请号：US786242
申请日：1991-10-31
申请人： Roger R. Lee , Fernando Gonzalez
发明人： Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： The invention is a product and method for forming the same comprising a storage contact capacitor of a DRAM device wherein the storage node capacitor plate comprises first and second capacitor portions. The first portion is a self-aligned Tungsten and TiN core. In a first embodiment the second portion is a storage node polysilicon deposited and subjected to an insitu phosphorus diffusion doping. In a second embodiment the second portion comprises tungsten fingers formed elevationally and horizontally to overlie the tungsten and TiN core. Portions of TiN provide spacing between adjacent tungsten fingers. An upper polysilicon layer functions as the upper capacitor plate and is insulated from the lower capacitor plate by a dielectric layer.
摘要翻译：本发明是一种用于形成DRAM器件的存储接触电容器的产品和方法，其中存储节点电容器板包括第一和第二电容器部分。第一部分是自对准钨和钛核。在第一实施例中，第二部分是沉积并经受现场磷扩散掺杂的存储节点多晶硅。在第二实施例中，第二部分包括形成为垂直和水平的钨指，以覆盖钨和TiN芯。 TiN的一部分提供相邻钨指之间的间距。上部多晶硅层用作上部电容器板，并通过介电层与下部电容器板绝缘。

74. 发明授权

US4446547A Record cleaning device 失效
标题翻译：记录清洁装置
公开(公告)号：US4446547A
公开(公告)日：1984-05-01
申请号：US339843
申请日：1982-01-18
申请人： Fernando Gonzalez
发明人： Fernando Gonzalez
IPC分类号： G11B3/58
CPC分类号： G11B3/5836
摘要： A record cleaning device which attaches to the tone arm of a record player for removing dust and other undesirable material from the grooves of a phonograph record without significant interferring with the normal tracking of the phonograph cartridge. The device includes a brush for brushing the undesirable material from the grooves of the phonograph record, and an elongated strip of thin, lightweight and flexible material for flexibly supporting the brush above and in contact with the grooves of the phonograph record in which the flexing action of the brush and that of the strip in relation to the brush weight allows for joint, commensurate and comparable flexing action of both during record playback. In a further embodiment a motion damper is mounted between the brush and the strip to stop energy exchange between them and to dampen feedback vibrations to the tone arm.
摘要翻译：记录清洁装置，其附接到记录播放器的色调臂，用于从留声机记录的凹槽除去灰尘和其它不期望的材料，而不会对留声机盒的正常跟踪造成明显的干扰。该装置包括用于从留声机记录槽的刷毛不需要的材料的刷子，以及一薄的，重量轻且柔软的材料的细长带，用于在留声机记录的凹槽上方柔性地支撑刷子，并与其中的弯曲动作的刷子和条带相对于刷子重量允许在记录回放期间两者的联合，相当和相当的弯曲动作。在另一实施例中，运动阻尼器安装在刷子和带之间，以阻止它们之间的能量交换并且抑制对音调臂的反馈振动。

75. 发明授权

US08501602B2 Method of manufacturing devices having vertical junction edge 有权
标题翻译：制造具有垂直接合边缘的器件的方法
公开(公告)号：US08501602B2
公开(公告)日：2013-08-06
申请号：US13336516
申请日：2011-12-23
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L21/425
CPC分类号： H01L29/66636 , H01L21/2257 , H01L21/823481 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/7834
摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
摘要翻译：用于形成诸如晶体管的器件的技术具有垂直的接合边缘。更具体地说，在沟槽中形成浅沟槽并填充氧化物。可以在氧化物中形成空穴并填充导电材料，例如掺杂的多晶硅。在沟槽边缘处在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望性质的二极管延伸。

76. 发明授权

US08173517B2 Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure 有权
标题翻译：用于形成利用侧壁间隔物作为蚀刻掩模并保留为隔离结构的一部分的自对准隔离结构的方法
公开(公告)号：US08173517B2
公开(公告)日：2012-05-08
申请号：US12828868
申请日：2010-07-01
申请人： Fernando Gonzalez , David L. Chapek , Randhir P. S. Thakur
发明人： Fernando Gonzalez , David L. Chapek , Randhir P. S. Thakur
IPC分类号： H01L21/764 , H01L29/00
CPC分类号： H01L21/76237
摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.
摘要翻译：本发明涉及在半导体衬底中形成微电子结构的方法。该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。间隔物可以由绝缘材料形成。隔离沟蚀刻遵循间隔物蚀刻。可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。保形材料的平面化可能遵循。

77. 发明授权

US08152758B2 Needle catheter 有权
标题翻译：针导管
公开(公告)号：US08152758B2
公开(公告)日：2012-04-10
申请号：US11841470
申请日：2007-08-20
申请人： Gregory Waimong Chan , Fernando Gonzalez , Thuhuong Thi Phan , Dwight A. Ambat , Manolo Lumauig , Mina W. Chow
发明人： Gregory Waimong Chan , Fernando Gonzalez , Thuhuong Thi Phan , Dwight A. Ambat , Manolo Lumauig , Mina W. Chow
IPC分类号： A61M29/00
CPC分类号： A61M29/00
摘要： An apparatus including an expandable body; at least one delivery cannula coupled to an exterior portion of the expandable body; a needle having a protuberance thereon disposed in a lumen of the at least one delivery cannula; a stop disposed in the lumen of the at least one delivery cannula at a position distal to the protuberance on the needle. A method including positioning a catheter assembly including at least one needle delivery device disposed in an at least one delivery cannula, the at least one delivery cannula having an exit end; modifying the shape of the catheter assembly to modify the orientation of the exit end of the at least one delivery cannula at a region of interest; and advancing the at least one needle delivery device beyond the exit end of the at least one delivery cannula according to a controlled orientation.
摘要翻译：一种包括可膨胀体的装置; 至少一个输送插管，其连接到所述可膨胀体的外部部分; 其上具有突起的针，其设置在所述至少一个输送插管的内腔中; 设置在所述至少一个输送套管的内腔中的位于远离所述针头上的突起的位置处的止动件。一种方法，包括定位包括设置在至少一个输送插管中的至少一个针递送装置的导管组件，所述至少一个输送插管具有出口端; 改变导管组件的形状以改变感兴趣区域中至少一个输送插管的出口端的取向; 以及根据受控的取向将所述至少一个针输送装置推进到所述至少一个输送插管的出口端。

78. 发明授权

US07919800B2 Capacitor-less memory cells and cell arrays 有权
标题翻译：无电容的存储单元和单元阵列
公开(公告)号：US07919800B2
公开(公告)日：2011-04-05
申请号：US11711449
申请日：2007-02-26
申请人： Fernando Gonzalez , Chandra V. Mouli
发明人： Fernando Gonzalez , Chandra V. Mouli
IPC分类号： H01L27/108 , H01L29/94 , H01L27/088
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译：无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。在有源区上形成传输晶体管，用于与字线耦合。无电容器存储单元还包括沿着有源区的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域有效区域，导致传输晶体管的不同可确定的阈值电压。

79. 发明授权

US07852668B2 Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell 有权
标题翻译：将磁性隧道结集成在浮动栅极存储单元上方的半导体磁存储器
公开(公告)号：US07852668B2
公开(公告)日：2010-12-14
申请号：US12360496
申请日：2009-01-27
申请人： Parag Banerjee , Terry Gafron , Fernando Gonzalez
发明人： Parag Banerjee , Terry Gafron , Fernando Gonzalez
IPC分类号： G11C11/15
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C16/0483 , H01L27/11521
摘要： A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
摘要翻译：半导体磁存储器件具有形成在存储单元上的磁性隧道结。存储单元具有由浮动栅极包围的控制栅极。浮动栅极通过钉扎层耦合到磁性隧道结，该钉扎层保持结的下部磁性层的磁性取向。耦合到控制栅极的选定字线的电流产生第一磁场。通过单元选择线的电流产生与第一磁场正交的第二磁场。这改变了结的上部磁性层的磁性取向以降低其电阻，从而允许编程/擦除线上的写入/擦除电压对浮动栅极进行编程/擦除。

80. 发明授权

US07678678B2 Method to chemically remove metal impurities from polycide gate sidewalls 有权
标题翻译：从多孔化合物侧壁化学去除金属杂质的方法
公开(公告)号：US07678678B2
公开(公告)日：2010-03-16
申请号：US11494844
申请日：2006-07-28
申请人： Fernando Gonzalez , Don Carl Powell
发明人： Fernando Gonzalez , Don Carl Powell
IPC分类号： H01L21/336
CPC分类号： H01L29/4941 , H01L21/02071 , H01L21/28061 , H01L21/28247 , H01L21/3185 , H01L21/3205 , H01L21/32051 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.
摘要翻译：一个实施方案包括形成栅极堆叠的过程，其用于抵抗例如从金属栅电极的移动的金属的半导体基板的再沉积。实施例还涉及实现该过程的系统。一个实施方案还涉及提供在加工和现场使用期间抵抗金属再沉积的组合物的栅极堆叠结构。

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