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71. 发明申请

US20070083717A1 Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response 失效
标题翻译：链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行进行顺序同步访问
公开(公告)号：US20070083717A1
公开(公告)日：2007-04-12
申请号：US11245313
申请日：2005-10-06
申请人： Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
发明人： Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0822
摘要： A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.
摘要翻译：一种方法和数据处理系统，用于在数据在链中的第一处理器的高速缓存中接收之前，将链接中的高速缓存行的连续的均匀处理器请求顺序耦合。分配链接的中间一致性状态，以便在启动链路的第一个处理器接收到数据之前跟踪处理器请求链和后续访问权限。所分配的链接中间一致性状态标识处理器操作，并且方向标识符标识要向其转发高速缓存行的处理器。当在链中的第一处理器的高速缓存处接收数据时，第一处理器完成其数据处理（或与数据）的操作，然后将数据转发到链中的下一个处理器。当最后一个链接处理器窥探非均匀操作时，链条立即停止。

72. 发明申请

US20060277370A1 Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout 有权
公开(公告)号：US20060277370A1
公开(公告)日：2006-12-07
申请号：US11146443
申请日：2005-06-06
申请人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.

73. 发明申请

US20060271742A1 Data processing system, cache system and method for actively scrubbing a domain indication 失效
公开(公告)号：US20060271742A1
公开(公告)日：2006-11-30
申请号：US11136651
申请日：2005-05-24
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F12/0822
摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.

74. 发明申请

US20060190910A1 Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs 有权
公开(公告)号：US20060190910A1
公开(公告)日：2006-08-24
申请号：US11408583
申请日：2006-04-21
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.

75. 发明申请

US20060184748A1 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
公开(公告)号：US20060184748A1
公开(公告)日：2006-08-17
申请号：US11056740
申请日：2005-02-11
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

76. 发明申请

US20060179226A1 System and method of re-ordering store operations within a processor 失效
标题翻译：在处理器内重新排序存储操作的系统和方法
公开(公告)号：US20060179226A1
公开(公告)日：2006-08-10
申请号：US11054450
申请日：2005-02-09
申请人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
发明人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/3824 , G06F12/0817
摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.
摘要翻译：一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功通过RC调度逻辑调度到RC机器。

77. 发明申请

US20060122818A1 Method, system and program product for defining and recording threshold-qualified count events of a simulation by testcases 失效
标题翻译：方法，系统和程序产品，用于通过测试案例定义和记录模拟的阈值限定计数事件
公开(公告)号：US20060122818A1
公开(公告)日：2006-06-08
申请号：US11006093
申请日：2004-12-07
申请人： Michael Behm , Carol Gabele , Wolfgang Roesner , Derek Williams
发明人： Michael Behm , Carol Gabele , Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a one method of simulation processing, a count event counter for a count event is created within instrumentation of a hardware description language (HDL) simulation model of a design and a threshold greater than 1 is established for the count event counter. The design is then simulated utilizing the HDL simulation model, and occurrences of the count event are accumulated in the count event counter to obtain a count event value. Thereafter, an indication of whether the count event value of the count event exceeds the threshold is recorded within a data storage subsystem.
摘要翻译：根据模拟处理的一种方法，在设计的硬件描述语言（HDL）仿真模型的仪表内创建计数事件的计数事件计数器，并为计数事件计数器建立大于1的阈值。然后利用HDL仿真模型对该设计进行仿真，并且计数事件的发生被累积在计数事件计数器中以获得计数事件值。此后，计数事件的计数事件值是否超过阈值的指示被记录在数据存储子系统内。

78. 发明申请

US20060095691A1 Processor, method, and data processing system employing a variable store gather window 有权
标题翻译：处理器，方法和数据处理系统采用变量存储收集窗口
公开(公告)号：US20060095691A1
公开(公告)日：2006-05-04
申请号：US10922272
申请日：2004-08-19
申请人： Robert Bell , Hugh Shen , Jeffrey Stuecheli , Derek Williams
发明人： Robert Bell , Hugh Shen , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

79. 发明申请

US20060089827A1 Method, system and program product for defining and recording minium and maximum event counts of a simulation utilizing a high level language 有权
标题翻译：用于使用高级语言定义和记录最小化和最大事件计数的方法，系统和程序产品
公开(公告)号：US20060089827A1
公开(公告)日：2006-04-27
申请号：US10970469
申请日：2004-10-21
申请人： Carol Gabele , Wolfgang Roesner , Derek Williams
发明人： Carol Gabele , Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.
摘要翻译：根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。然后接收并处理从模拟设计获得的仿真结果数据。在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。

80. 发明申请

US20060085604A1 Processor, data processing system and method for synchronizing access to data in shared memory 失效
标题翻译：处理器，数据处理系统和方法，用于同步共享存储器中数据的访问
公开(公告)号：US20060085604A1
公开(公告)日：2006-04-20
申请号：US10965144
申请日：2004-10-14
申请人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
发明人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/3851 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.
摘要翻译：一种用于多处理器数据处理系统的处理单元，包括处理器核心，该处理器核心包括通过存储的上级高速缓存，指令执行指令排序单元，数据寄存器以及耦合到指令排序单元的至少一个指令执行单元，同时执行多个指令线程。所述处理器核心响应于所述至少一个指令执行单元在与冲突存储条件相关联的预留危险窗口期间执行在所述存储通过上级高速缓存中的绑定到加载目标地址的第一线程中的加载保留指令如果第二线程的存储条件操作成功，则第二线程的操作使得第一线程的后续存储条件操作到与加载目标地址匹配的存储目标地址失败。

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