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71. 发明授权

US6061236A Computer component carrier that directs airflow to critical components 失效
标题翻译：将气流引导到关键部件的计算机组件载体
公开(公告)号：US6061236A
公开(公告)日：2000-05-09
申请号：US848528
申请日：1997-04-28
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F1/20 , H05K7/20 , H05H7/20
CPC分类号： G06F1/20
摘要： A computer component carrier isolates components from vibration, reduces noise, reduces assembly time, improves airflow to critical components, and reduces EMI. The component carrier is fabricated from a vibration damping material such as urethane foam. The component carrier contains cavities to accommodate electronic components. These cavities are interconnected via airways that direct airflow between the cavities. The component carrier includes two or more pieces. Components are placed in the cavities of the component carrier designed to accommodate the components and the pieces of the component carrier are mated and secured. In this manner, the components are firmly held in position by the component carrier. The component carrier can be fabricated with a hard exterior finish that replaces a computer casing or cabinet. The component carrier can also be fabricated from a recyclable and/or recycled material.
摘要翻译：计算机组件载体将组件与振动隔离，减少噪音，减少组装时间，改善关键部件的气流，并降低EMI。部件载体由诸如聚氨酯泡沫的减振材料制成。组件载体包含容纳电子部件的空腔。这些空腔通过气道相互连接，该空气导引空腔之间的气流。部件载体包括两个或更多个部件。组件被放置在组件载体的空腔中，设计成容纳部件并且部件载体的部件配合和固定。以这种方式，部件通过部件载体牢固地保持就位。组件载体可以制造成具有硬的外观，代替计算机外壳或机柜。组分载体也可以由可回收和/或再循环材料制成。

72. 发明授权

US6047381A Variable speed controller 失效
标题翻译：变速控制器
公开(公告)号：US6047381A
公开(公告)日：2000-04-04
申请号：US925885
申请日：1997-09-08
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： A variable speed controller is disclosed that is capable of processing selected commands at a faster-than-normal rate. The invention is useful in the context of x86-based microcomputers to speed up the execution of MASK-A20 and/or RESET-CPU commands that are normally carried out by an 8042-based controller. Execution time for these operations is improved, yet compatibility with existing peripherals and/or code is retained.
摘要翻译：公开了一种能够以比正常速率更快地处理选定命令的变速控制器。本发明在基于x86的微型计算机的上下文中是有用的，以加速通常由基于8042的控制器执行的MASK-A20和/或RESET-CPU命令的执行。这些操作的执行时间得到改善，但仍保留与现有外设和/或代码的兼容性。

73. 发明授权

US6044427A Upgradable mobile processor module and method for implementing same 失效
标题翻译：可升级移动处理器模块及其实现方法
公开(公告)号：US6044427A
公开(公告)日：2000-03-28
申请号：US15866
申请日：1998-01-29
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4068
摘要： A method for preparing an upgradable Pentium-based mobile processor module that is forward-compatible with an enhanced Pentium II-based mobile processor module. The upgradable Pentium-based mobile processor module uses 0.5 millimeter pitch connection technology and contains a system controller that supports a single peripheral component interconnect port. The upgradable Pentium-based mobile processor module provides a PCI port for connection to a PCI bus and an AGP port for connection to an AGP bus. The AGP port is electronically connected to the PCI port so that both the AGP port and the PCI port receive data and control signals from the system controller according to the PCI protocol standard.
摘要翻译：一种用于准备与基于增强型Pentium II的移动处理器模块前向兼容的可升级的基于奔腾的移动处理器模块的方法。可升级的基于Pentium的移动处理器模块使用0.5毫米间距连接技术，并包含支持单个外围组件互连端口的系统控制器。可升级的基于奔腾的移动处理器模块提供了一个PCI端口，用于连接到PCI总线和AGP端口，用于连接到AGP总线。 AGP端口电连接到PCI端口，使AGP端口和PCI端口根据PCI协议标准从系统控制器接收数据和控制信号。

74. 发明授权

US06038672A Portable computer with low power CD-player mode 失效
公开(公告)号：US06038672A
公开(公告)日：2000-03-14
申请号：US6090
申请日：1998-01-13
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/32
摘要： A power-conserving computer containing a peripheral device that, when used alone, requires the CPU of the computer to be powered-on for only the short period of time needed for the CPU to translate a user-specified command into a command that the CPU then transmits to the peripheral device. Inputs are added to the computer system for direct input of user commands to the peripheral device. The BIOS power-up/reset routine of the computer is modified to detect power-on as a result of user input to the added inputs, to then transmit a corresponding command to the peripheral device, and to finally power down the CPU. The system controller of the computer is electrically shielded from the peripheral device when the system controller is powered-down and the peripheral device is operating.

75. 发明授权

US6029223A Advanced programmable interrupt controller 失效
标题翻译：高级可编程中断控制器
公开(公告)号：US6029223A
公开(公告)日：2000-02-22
申请号：US67338
申请日：1998-04-27
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A computer system having an advanced programmable interrupt controller (APIC) is described in which an I/O APIC module is included in core logic circuitry coupled between a processor bus and a system bus. An interrupt controller is included in bridge circuitry coupled between the system bus and an expansion bus. System and expansion bus devices requiring service output interrupt request signals (IRQs) which are received by the interrupt controller. The interrupt controller then outputs an interrupt signal which is received by the I/O APIC module. The I/O APIC module initiates a system bus acknowledge cycle to receive an interrupt vector from the interrupt controller. The I/O APIC module converts the interrupt vector into a system-appropriate APIC protocol and transmits the vector on an APIC bus to local APIC modules integrated within processors of the computer system. In one embodiment, the I/O APIC module receives the system bus device IRQs directly, and the system bus acknowledge cycle is required only to obtain the expansion bus device interrupt vectors.
摘要翻译：描述了具有高级可编程中断控制器（APIC）的计算机系统，其中I / O APIC模块被包括在耦合在处理器总线和系统总线之间的核心逻辑电路中。一个中断控制器被包括在耦合在系统总线和扩展总线之间的桥接电路中。系统和扩展总线设备需要中断控制器接收的服务输出中断请求信号（IRQ）。然后中断控制器输出由I / O APIC模块接收的中断信号。 I / O APIC模块启动系统总线确认周期，以从中断控制器接收中断向量。 I / O APIC模块将中断向量转换为系统适合的APIC协议，并将APIC总线上的矢量传输到集成在计算机系统处理器内的本地APIC模块。在一个实施例中，I / O APIC模块直接接收系统总线设备IRQ，并且仅需要系统总线确认周期才能获得扩展总线设备中断向量。

76. 发明授权

US6026463A Method for improving data transfer rates for user data stored on a disk storage device 失效
标题翻译：用于提高存储在磁盘存储设备上的用户数据的数据传输速率的方法
公开(公告)号：US6026463A
公开(公告)日：2000-02-15
申请号：US927233
申请日：1997-09-10
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F3/06 , G11B20/12 , G11B27/32 , G06F12/02
CPC分类号： G06F3/0613 , G06F3/0638 , G06F3/0674 , G11B20/12 , G11B20/1258 , G11B27/329 , G11B2020/1232 , G11B2020/1267 , G11B2220/2516
摘要： The overall transfer rate of user data is improved with the translation of certain low-number logical addresses into higher number physical addresses in order to displace inward the low-number logical data (e.g., low-level data). This makes it possible to store at least some user data on the higher transfer rate, outer cylinders. The sequence of the resulting physical addresses is changed relative to the logical addresses.
摘要翻译：通过将某些低数量逻辑地址转换为较高数量的物理地址以便向内移位低数量逻辑数据（例如，低级数据），用户数据的总传输速率得到改善。这使得可以在较高传送速率的外部柱面上存储至少一些用户数据。所产生的物理地址的顺序相对于逻辑地址而改变。

77. 发明授权

US6011541A Dual pointing device 失效
标题翻译：双指点设备
公开(公告)号：US6011541A
公开(公告)日：2000-01-04
申请号：US843289
申请日：1997-04-11
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F1/16 , G06F3/038 , G06F3/00
CPC分类号： G06F3/038 , G06F1/1616 , G06F1/169
摘要： The present invention relates to an apparatus for enabling a user to make a seamless transition between using a primary pointing device and a secondary pointing device on a computer to interact with the computer. The apparatus comprises a first microcontroller and a second microcontroller, wherein the first and second microcontrollers are electrically connected to each other. A primary pointing device input is connected to the first microcontroller, and a secondary pointing device input is connected to the second microcontroller. A system microcontroller is electrically connected to the first microcontroller. The first and second microcontrollers share a first and second switch. Computer software instructions operative by the first microcontroller determine which of the primary pointing device and the secondary pointing device is in use. If the primary pointing device is in use, then the first microcontroller process the switch actions (i.e., the data from the primary pointing device input element). The processed data output by the first microcontroller is transmitted by the first microcontroller to the system microcontroller.If the secondary pointing device is in use, then the software operative by the first microcontroller causes the first microcontroller to ignore the switch actions. By ignoring the switch actions, the data processed by the second microcontroller, which is sent to the first microcontroller, is transmitted to the system microcontroller. Thus, this apparatus enables a use to make a seamless transition between the primary and secondary pointing device and use either pointing device at any time.
摘要翻译：本发明涉及一种用于使用户能够在计算机上使用主要指点设备和次要指点设备之间进行无缝转换以与计算机交互的装置。该装置包括第一微控制器和第二微控制器，其中第一和第二微控制器彼此电连接。主要指点设备输入连接到第一微控制器，并且辅助指示设备输入连接到第二微控制器。系统微控制器电连接到第一微控制器。第一和第二微控制器共享第一和第二开关。由第一微控制器操作的计算机软件指令确定主要指示装置和辅助指示装置中的哪个正在使用。如果主要指点装置正在使用，则第一微控制器处理开关动作（即，来自主要指点装置输入元件的数据）。由第一微控制器输出的经处理的数据由第一微控制器传输到系统微控制器。如果辅助指示设备正在使用，则由第一微控制器操作的软件使得第一微控制器忽略开关动作。通过忽略开关动作，被发送到第一微控制器的由第二微控制器处理的数据被传送到系统微控制器。因此，该装置能够用于在主指示装置和辅助指示装置之间进行无缝转换，并且可以随时使用指示装置。

78. 发明授权

US6006310A Single memory device that functions as a multi-way set associative cache memory 失效
标题翻译：用作多路组关联高速缓存的单一存储器件
公开(公告)号：US6006310A
公开(公告)日：1999-12-21
申请号：US531134
申请日：1995-09-20
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G11C7/10 , G11C8/12 , G06F12/00
CPC分类号： G06F12/0864 , G11C7/1018 , G11C7/103 , G11C8/12
摘要： A memory device provides for multi-way set associative burst SRAM (static random access memory) cache memory in a single device or package. In one embodiment input address bit A2 is used to generate a bank select signal rather than as a direct input to the SRAM's memory array element. This, in combination with additional output registers and output buffers creates a two-way set associative cache memory in a single memory device. In an alternative embodiment, input address bits A2 and A3 are used to generate bank select signals rather than as direct input to the SRAM's memory array element. This, in combination with additional output registers, output buffers, and an output bank decoder creates a four-way set associative cache memory in a single memory device. Additionally, a mode circuit is provided that controls whether the memory device operates as a multi-way set associative memory or as a conventional direct-mapped memory device. The mode circuit provides backwards compatibility with existing burst SRAM devices.
摘要翻译：存储器件在单个器件或封装中提供多路组合关联突发SRAM（静态随机存取存储器）高速缓冲存储器。在一个实施例中，输入地址位A2用于产生存储体选择信号而不是作为对SRAM存储器阵列元件的直接输入。这与额外的输出寄存器和输出缓冲器组合在单个存储器件中创建双向组关联高速缓冲存储器。在替代实施例中，输入地址位A2和A3用于产生存储体选择信号，而不是作为对SRAM存储器阵列元件的直接输入。这与附加输出寄存器，输出缓冲器和输出组解码器组合在单个存储器件中创建四路组关联高速缓冲存储器。此外，提供了一种模式电路，其控制存储器件是作为多路组合关联存储器还是作为传统的直接映射存储器件。模式电路提供与现有突发SRAM器件的向后兼容性。

79. 发明授权

US5974239A Data transfer method for a bus device in a computer system by placing first and second addresses corresponding to a bridge and with the bus device respectively on a bus 失效
标题翻译：通过将对应于桥接器和总线设备的第一和第二地址分别放置在总线上的计算机系统中的总线设备的数据传输方法
公开(公告)号：US5974239A
公开(公告)日：1999-10-26
申请号：US873213
申请日：1997-06-11
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4027
摘要： A PCI/ISA computer system architecture is disclosed in which the ISA legacy circuitry (such as the interrupt request controller, DMA controller, and timer counter unit) is integrated within the system controller coupling the processor and PCI buses. Accordingly, the ISA bridge coupling the PCI and ISA buses is simplified relative to prior art PCI-ISA bridges. A high speed communications channel between the system controller and the ISA bridge is established by first placing an address on the PCI bus which is recognizable only by the system controller and the ISA bridge. Data transfer then occurs within standard PCI protocols, but need only require a subset of the A/D lines. Backwards compatibility is maintained, while system performance is improved and system cost is reduced.
摘要翻译：公开了PCI / ISA计算机系统架构，其中ISA遗留电路（例如中断请求控制器，DMA控制器和定时器计数器单元）集成在耦合处理器和PCI总线的系统控制器内。因此，耦合PCI和ISA总线的ISA桥相对于现有技术的PCI-ISA桥简化。系统控制器和ISA桥之间的高速通信通道首先在PCI总线上放置一个只能由系统控制器和ISA桥接器识别的地址。数据传输然后发生在标准PCI协议中，但只需要A / D线的一个子集。维持向后兼容性，同时提高系统性能，降低系统成本。

80. 发明授权

US5931937A Symmetric parallel multi-processing bus architecture 失效
标题翻译：对称并行多处理总线架构
公开(公告)号：US5931937A
公开(公告)日：1999-08-03
申请号：US948802
申请日：1997-10-10
申请人： Dean A. Klein
发明人： Dean A. Klein
IPC分类号： G06F13/26 , G06F9/46
CPC分类号： G06F13/26
摘要： An apparatus for and method of coupling a number of data processing components onto a bus for communication amongst the components with a symmetric parallel multi-processing bus system architecture. The bus architecture is particularly applicable to micro computer systems for the interconnection of processing units, memories, and peripherals. The function of arbitration is distributed within the users of the bus permitting ease of coupling relatively slow and fast devices to the same bus. Bus access priority may be easily modified either semi-permanently or by way of rotation.
摘要翻译：一种用于将多个数据处理组件耦合到总线上的装置和方法，用于在具有对称并行多处理总线系统架构的组件之间进行通信。总线架构特别适用于处理单元，存储器和外围设备互连的微型计算机系统。仲裁的功能分布在总线的用户中，从而可以将相对较慢和快速的设备耦合到同一总线。总线访问优先级可以容易地被修改为半永久地或通过轮换。

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