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71. 发明授权

US08476160B2 Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall 失效
标题翻译：使用可控制损坏的电介质侧壁的图像转印的光刻图案
公开(公告)号：US08476160B2
公开(公告)日：2013-07-02
申请号：US12913116
申请日：2010-10-27
申请人： Shom Ponoth , David V. Horak , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/02126 , H01L21/3105 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.
摘要翻译：第一低介电常数（低k）电介质材料层被光刻图案化以形成具有暴露基本上垂直侧壁的凹陷区域，其随后被损坏以使具有亚光刻宽度的侧壁处的表面部分脱碳。沉积第二低k电介质材料层以填充凹陷区域并平坦化到损坏的低k电介质材料部分的暴露的顶表面。选择性地去除损坏的低k电介质材料部分到第一和第二低k电介质材料层以形成具有亚光刻宽度的沟槽。亚光刻宽度沟槽的图案的一部分被转移到金属层中，并且可选地转移到下面的介电掩模材料层以限定具有亚光刻宽度的沟槽，其可以用作模板以限制通孔的宽度和随后在互连级介电材料层中形成线沟槽。

72. 发明授权

US08227339B2 Creation of vias and trenches with different depths 失效
标题翻译：创造不同深度的通道和沟渠
公开(公告)号：US08227339B2
公开(公告)日：2012-07-24
申请号：US12610624
申请日：2009-11-02
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L21/3065
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
摘要翻译：本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。还提供了由此制成的半导体结构。

73. 发明授权

US08211776B2 Integrated circuit line with electromigration barriers 失效
标题翻译：集成电路线与电迁移障碍
公开(公告)号：US08211776B2
公开(公告)日：2012-07-03
申请号：US12652485
申请日：2010-01-05
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译：一种用于制造集成电路的集成电路的方法，包括：集成电路的一行中的电迁移势垒包括形成间隔物; 形成与所述间隔物的相对侧相邻的分段线，所述分段线由第一导电材料形成; 移除间隔物以形成空线断裂; 并用第二导电材料填充空线断裂以形成电隔离屏蔽，其隔离分段线的各个段内的电迁移效应。包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料线路各部分的电迁移效应。

74. 发明申请

US20110018093A1 PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER 失效
标题翻译： DLC介电层可编程防结构
公开(公告)号：US20110018093A1
公开(公告)日：2011-01-27
申请号：US12509892
申请日：2009-07-27
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.
摘要翻译：在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域第一电介质材料。反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性材料在第二个反熔丝区域。在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。第二电介质材料包括嵌入其中的至少一个导电填充区域。

75. 发明申请

US20100264543A1 INTERCONNECT STRUCTURE 有权
标题翻译：互连结构
公开(公告)号：US20100264543A1
公开(公告)日：2010-10-21
申请号：US12424843
申请日：2009-04-16
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76847 , H01L21/76805 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.
摘要翻译：公开了用于形成半导体互连结构的互连结构和方法。在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

76. 发明授权

US08124525B1 Method of forming self-aligned local interconnect and structure formed thereby 失效
标题翻译：形成自对准局部互连和由此形成的结构的方法
公开(公告)号：US08124525B1
公开(公告)日：2012-02-28
申请号：US12913143
申请日：2010-10-27
申请人： Charles W. Koburger, III , David V. Horak , Shom Pomoth , Chih-Chao Yang , Su Chen Fan , Sivananda K. Kanakasabapathy
发明人： Charles W. Koburger, III , David V. Horak , Shom Pomoth , Chih-Chao Yang , Su Chen Fan , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/7682 , H01L21/76895 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a method of forming local interconnect for semiconductor devices. The method includes depositing a blanket layer of conductive material over one or more semiconductor devices; creating a pattern of local interconnect covering a portion of the blanket layer of conductive material; removing rest of the blanket layer of conductive material that is not covered by the pattern of local interconnect; forming the local interconnect by the portion of the blanket layer of conductive material to connect the one or more semiconductor devices.
摘要翻译：本发明的实施例提供一种形成用于半导体器件的局部互连的方法。该方法包括在一个或多个半导体器件上沉积导电材料的覆盖层; 产生覆盖导电材料的覆盖层的一部分的局部互连图案; 去除未被局部互连图案覆盖的导电材料的覆盖层的其余部分; 通过导电材料的覆盖层的部分形成局部互连以连接一个或多个半导体器件。

77. 发明授权

US09105693B2 Microelectronic structure including air gap 有权
标题翻译：微电子结构包括气隙
公开(公告)号：US09105693B2
公开(公告)日：2015-08-11
申请号：US13614563
申请日：2012-09-13
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L29/40 , H01L21/4763 , H01L21/768
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
摘要翻译：微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。多个空隙也位于衬垫层和层间电介质层之间。空隙提供了微电子结构的增强的电性能。

78. 发明申请

US20140070282A1 SELF-ALIGNED CONTACTS 有权
标题翻译：自对准联系人
公开(公告)号：US20140070282A1
公开(公告)日：2014-03-13
申请号：US13607856
申请日：2012-09-10
申请人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
发明人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要翻译：本文公开了金属栅极结构中的自对准触点和制造方法。该方法包括形成具有侧壁结构的金属栅极结构。该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

79. 发明授权

US07943480B2 Sub-lithographic dimensioned air gap formation and related structure 有权
标题翻译：亚光刻尺寸气隙形成及相关结构
公开(公告)号：US07943480B2
公开(公告)日：2011-05-17
申请号：US12029800
申请日：2008-02-12
申请人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
发明人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L23/00
CPC分类号： H01L21/7682 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.
摘要翻译：公开了亚光刻尺寸气隙形成和相关结构。在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

80. 发明授权

US08853076B2 Self-aligned contacts 有权
标题翻译：自对准接触
公开(公告)号：US08853076B2
公开(公告)日：2014-10-07
申请号：US13607856
申请日：2012-09-10
申请人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
发明人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
IPC分类号： H01L21/44
CPC分类号： H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要翻译：本文公开了金属栅极结构中的自对准触点和制造方法。该方法包括形成具有侧壁结构的金属栅极结构。该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

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