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71. 发明申请

US20050246481A1 Memory controller with command queue look-ahead 有权
标题翻译：带有命令队列的内存控制器
公开(公告)号：US20050246481A1
公开(公告)日：2005-11-03
申请号：US10834597
申请日：2004-04-28
申请人： Natarajan Rohit , Debra Bernstein , Gilbert Wolrich , Chang-Ming Lin
发明人： Natarajan Rohit , Debra Bernstein , Gilbert Wolrich , Chang-Ming Lin
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/161
摘要： In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in part, on the memory access operations identified by the commands and the memory access operation of a previously selected memory access command
摘要翻译：通常，在一个方面，本公开描述了从与随机存取存储器（RAM）的相应的存储体组相关联的多个存储器访问命令队列之一访问多个存储器访问命令，并且至少部分地基于所述命令来选择一个命令关于由命令识别的存储器访问操作和先前选择的存储器访问命令的存储器访问操作

72. 发明申请

US20050216656A1 Content addressable memory to identify subtag matches 失效
标题翻译：内容可寻址内存，用于标识子标签匹配
公开(公告)号：US20050216656A1
公开(公告)日：2005-09-29
申请号：US10811288
申请日：2004-03-25
申请人： Mark Rosenbluth , Gilbert Wolrich
发明人： Mark Rosenbluth , Gilbert Wolrich
IPC分类号： G06F12/00 , G11C15/00
CPC分类号： G11C15/00
摘要： The disclosure includes a description of a content addressable memory (CAM) that includes at least one tag input and at least one random access memory. The CAM also includes circuitry to perform multiple read operations of the at least one random access memory with multiple, different ones of the read operations specifying an address based on different subsets of tag bits. The circuitry includes digital logic circuitry coupled to the at least one random access memory to determine whether a lookup tag matches a subset of the different subsets of tag bits.
摘要翻译：本公开包括对包括至少一个标签输入和至少一个随机存取存储器的内容可寻址存储器（CAM）的描述。 CAM还包括用于执行具有多个不同的读取操作的至少一个随机存取存储器的多次读取操作的电路，其基于标签位的不同子集指定地址。电路包括耦合到至少一个随机存取存储器的数字逻辑电路，以确定查找标签是否与标签位的不同子集的子集相匹配。

73. 发明申请

US20050185437A1 Memory interleaving 有权
公开(公告)号：US20050185437A1
公开(公告)日：2005-08-25
申请号：US11112047
申请日：2005-04-22
申请人： Gilbert Wolrich , Mark Rosenbluth
发明人： Gilbert Wolrich , Mark Rosenbluth
IPC分类号： G06F12/06 , G11C15/00
CPC分类号： G06F12/0607
摘要： Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

74. 发明申请

US20050141715A1 Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor 失效
标题翻译：用于在可编程网络处理器中调度由密码算法核心执行的命令的处理的方法和装置
公开(公告)号：US20050141715A1
公开(公告)日：2005-06-30
申请号：US10747852
申请日：2003-12-29
申请人： Jaroslaw Sydir , Chen-Chi Kuo , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Chen-Chi Kuo , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： H04K1/00
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.
摘要翻译：一种用于通过网络处理器中的多个加密算法核心调度命令处理的方法和装置。

75. 发明申请

US20050138368A1 Method and apparatus for performing an authentication after cipher operation in a network processor 有权
标题翻译：在网络处理器中进行密码操作之后进行认证的方法和装置
公开(公告)号：US20050138368A1
公开(公告)日：2005-06-23
申请号：US10741676
申请日：2003-12-19
申请人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： H04L9/06 , H04L9/18 , H04L9/32 , H04L29/06 , H04L9/00
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.
摘要翻译：描述了一种方法和装置，用于通过具有对网络数据分组内的数据进行操作的密码处理核和认证处理核的网络处理器来处理网络数据分组，以便提供网络数据的一次通过加密和认证处理数据包

76. 发明申请

US20050010761A1 High performance security policy database cache for network processing 审中-公开
标题翻译：用于网络处理的高性能安全策略数据库缓存
公开(公告)号：US20050010761A1
公开(公告)日：2005-01-13
申请号：US10618576
申请日：2003-07-11
申请人： Alwyn Dos Remedios , Wajdi Feghali , Gilbert Wolrich , Bradley Burres
发明人： Alwyn Dos Remedios , Wajdi Feghali , Gilbert Wolrich , Bradley Burres
IPC分类号： H04L29/06 , H04L9/00
CPC分类号： H04L63/0485 , H04L63/164
摘要： A security policy database cache includes at least one primary table including signature values that indicate that a packet's security policy database information may be in the cache and at least one secondary table including cache entries having a selector, flags, security association information and an operation to perform on the corresponding packet for which a cache lookup was made.
摘要翻译：安全策略数据库高速缓存包括至少一个主表，其包括指示分组的安全策略数据库信息可以在高速缓存中的签名值，以及包括具有选择器，标志，安全关联信息和操作的高速缓存条目的至少一个辅助表对进行高速缓存查找的相应数据包执行。

77. 发明授权

US06681300B2 Read lock miss control and queue management 有权
标题翻译：读锁定错误控制和队列管理
公开(公告)号：US06681300B2
公开(公告)日：2004-01-20
申请号：US09969436
申请日：2001-10-02
申请人： Gilbert Wolrich , Daniel Cutter , William Wheeler , Matthew J. Adiletta , Debra Bernstein
发明人： Gilbert Wolrich , Daniel Cutter , William Wheeler , Matthew J. Adiletta , Debra Bernstein
IPC分类号： G06F1200
CPC分类号： G06F9/52
摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.
摘要翻译：管理对随机存取存储器的存储器访问包括获取读取锁定存储器引用请求并将读取的锁定存储器引用请求放置在读取锁定未命中队列的结尾，如果读取锁定存储器引用请求访问未锁定的存储器位置并读取锁定未命中队列至少包含一个读锁定存储器引用请求。

78. 发明授权

US06668311B2 Method for memory allocation and management using push/pop apparatus 有权
公开(公告)号：US06668311B2
公开(公告)日：2003-12-23
申请号：US09919058
申请日：2001-07-30
申请人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
发明人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
IPC分类号： G06F1200
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

79. 发明授权

US06661794B1 Method and apparatus for gigabit packet assignment for multithreaded packet processing 有权
标题翻译：用于多线程数据包处理的千兆位数据包分配的方法和装置
公开(公告)号：US06661794B1
公开(公告)日：2003-12-09
申请号：US09474650
申请日：1999-12-29
申请人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , Donald F. Hooper
发明人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , Donald F. Hooper
IPC分类号： H04L1256
CPC分类号： H04L49/351 , H04L49/102 , H04L49/352
摘要： A network processor that has multiple processing elements, each processing element supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads, or a different program thread for segment of data in a packet. For the two program threads, one program thread can be used for header segment processing and the other program thread can be used for handling payload segment(s). Dedicated inputs for ready status and sequence numbers can provide assistance for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.
摘要翻译：具有多个处理元件的网络处理器，每个处理元件支持多个同时的程序线程，并且能够访问接口中的共享资源。分组数据从段中的高速端口接收，并且每个段被分配给程序线程之一。每个数据包可以分配给单个程序线程，两个程序线程，或者分组中的数据段的不同程序线程。对于两个程序线程，一个程序线程可用于头段处理，另一个程序线程可用于处理有效负载段。准备状态和序列号的专用输入可以帮助通过高速端口接收分组数据。专用输入用于逐个循环地监视来自高速端口的就绪标志。分配的线程使用序列号来维护分组中段的排序，以及命令将完整分组写入传送队列。

80. 发明授权

US06606704B1 Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode 有权
标题翻译：并行多线程处理器，具有执行多个线程的多个微引擎，每个微引擎具有可加载的微代码
公开(公告)号：US06606704B1
公开(公告)日：2003-08-12
申请号：US09387111
申请日：1999-08-31
申请人： Matthew J. Adiletta , Gilbert Wolrich , William Wheeler
发明人： Matthew J. Adiletta , Gilbert Wolrich , William Wheeler
IPC分类号： G06F924
CPC分类号： G06F9/30076 , G06F9/3004 , G06F9/3012 , G06F9/30127 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F15/8015
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

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