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71. 发明授权

US08362599B2 Forming radio frequency integrated circuits 有权
标题翻译：形成射频集成电路
公开(公告)号：US08362599B2
公开(公告)日：2013-01-29
申请号：US12566338
申请日：2009-09-24
申请人： Jonghae Kim , Brian M. Henderson , Matthew M. Nowak , Jiayu Xu
发明人： Jonghae Kim , Brian M. Henderson , Matthew M. Nowak , Jiayu Xu
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L23/645 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16235 , H01L2224/16265 , H01L2224/17181 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/19011 , H01L2924/19104 , H01L2924/3025 , H01L2924/00
摘要： Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate.
摘要翻译：提供了形成射频集成电路（RFIC）的方法。 RFIC包括形成在半导体衬底中的一个或多个电子器件和以堆叠方式布置的电介质衬底上的一个或多个无源器件。在屏蔽结构之间形成有屏蔽半导体衬底中的电子器件与电介质衬底中的无源器件。形成垂直通硅通孔（TSV）以提供电介质基板中的无源器件与半导体衬底中的电子器件之间的电连接。

72. 发明申请

US20130021305A1 PIEZOELECTRIC LATERALLY VIBRATING RESONATOR STRUCTURE GEOMETRIES FOR SPURIOUS FREQUENCY SUPPRESSION 有权
标题翻译：压电式横向振动谐振器结构几何形状的频率抑制
公开(公告)号：US20130021305A1
公开(公告)日：2013-01-24
申请号：US13186281
申请日：2011-07-19
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Jonghae Kim
IPC分类号： G09G5/00 , H01L41/22 , H01L41/047
CPC分类号： H03H9/02228 , H03H3/02 , H03H9/02055 , H03H9/173 , H03H2003/021 , Y10T29/42
摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a resonator structure includes a first conductive layer of electrodes and a second conductive layer of electrodes. A piezoelectric layer including a piezoelectric material is disposed between the first conductive layer and the second conductive layer. One or more trenches can be formed in the piezoelectric layer on one or both sides in space regions between the electrodes. In some implementations, a process for forming the resonator structure includes removing an exposed portion of the piezoelectric layer to define a trench, for instance, by partial etching or performing an isotropic release etch using a XeF2 gas or SF6 plasma. In some other implementations, a portion of a sacrificial layer is removed to define a trench in the piezoelectric layer.
摘要翻译：本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。一方面，谐振器结构包括电极的第一导电层和电极的第二导电层。包括压电材料的压电层设置在第一导电层和第二导电层之间。一个或多个沟槽可以在电极之间的空间区域的一侧或两侧的压电层中形成。在一些实施方案中，用于形成谐振器结构的工艺包括去除压电层的暴露部分以限定沟槽，例如通过部分蚀刻或使用XeF 2气体或SF 6等离子体进行各向同性释放蚀刻。在一些其他实施方案中，去除牺牲层的一部分以在压电层中限定沟槽。

73. 发明授权

US08359421B2 Partitioning a crossbar interconnect in a multi-channel memory system 有权
标题翻译：在多通道存储器系统中分隔交叉开关互连
公开(公告)号：US08359421B2
公开(公告)日：2013-01-22
申请号：US12536991
申请日：2009-08-06
申请人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
发明人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
IPC分类号： G06F13/00 , G06F12/00 , G06F15/16
CPC分类号： G06F13/1663 , G06F13/1684 , Y02D10/14
摘要： A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters.
摘要翻译：一种方法包括从多个主器件识别第一组主器件和第二组主器件。多个主机通过交叉开关互连访问多通道存储器。该方法包括将交叉开关互连划分成多个分区，其包括至少对应于第一组主机的第一分区和对应于第二组主机的第二分区。该方法还包括在多通道存储器内分配第一组缓冲区。第一组缓冲区对应于第一组主机。该方法还包括在多通道存储器内分配第二组缓冲区。第二组缓冲器对应于第二组主机。

74. 发明申请

US20120199949A1 High Density Metal-Insulator-Metal Trench Capacitor 有权
标题翻译：高密度金属绝缘子 - 金属沟槽电容器
公开(公告)号：US20120199949A1
公开(公告)日：2012-08-09
申请号：US13021151
申请日：2011-02-04
申请人： Je-Hsiung Lan , Matthew Michael Nowak , Evgeni P. Gousev , Jonghae Kim , Clarence Chui
发明人： Je-Hsiung Lan , Matthew Michael Nowak , Evgeni P. Gousev , Jonghae Kim , Clarence Chui
IPC分类号： H01L29/92 , H01L21/62
CPC分类号： H01L28/82 , H01G4/012 , H01G4/10 , H01L23/5223 , H01L23/642 , H01L28/87 , H01L29/945 , H01L2224/16225 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311
摘要： Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.
摘要翻译：通过增加电容器的表面积来实现更高的电容密度。可以通过在半导体管芯上的沟槽中形成各向同性球形（凹面）来获得更大的表面积。通过沉积非晶硅和氧化硅的双层来制造凹面。在用于沟槽的氧化硅硬掩模中图案化开口。通过各向同性蚀刻将开口转移到非晶硅层以形成凹面。导电，绝缘和导电层通过原子层沉积沉积在沟槽的凹面上。

75. 发明授权

US08093982B2 Three dimensional inductor and transformer design methodology of glass technology 有权
标题翻译：玻璃技术的三维电感和变压器设计方法
公开(公告)号：US08093982B2
公开(公告)日：2012-01-10
申请号：US12731393
申请日：2010-03-25
申请人： Jonghae Kim , Milind P. Shah , Chi Shun Lo , Je-Hsiung Lan , Xia Li , Matthew Michael Nowak
发明人： Jonghae Kim , Milind P. Shah , Chi Shun Lo , Je-Hsiung Lan , Xia Li , Matthew Michael Nowak
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F2017/004 , H01L21/84 , H01L23/645 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path.
摘要翻译：一种用于集成电路器件的电感器或变压器，其包括高电阻率衬底。电感器包括围绕衬底的多个导电迹线，形成从第一端口到第二端口的连续导电路径。导电路径可以是螺线管形的。一些导电迹线可以在集成电路管芯的后端处理或背面电镀期间形成。变压器包括具有输入和输出端口的第一电感器和它们之间的第一连续导电路径; 以及具有输入和输出端口的第二电感器以及它们之间的第二连续导电路径。第二电感器与第一电感器无关并与其电磁耦合。第一和第二导电路径可以是螺线管形的。第一导电路径可以与第二导电路径交错。

76. 发明申请

US20120001297A1 Techniques for Placement of Active and Passive Devices within a Chip 有权
标题翻译：主动和被动设备放置在芯片内的技术
公开(公告)号：US20120001297A1
公开(公告)日：2012-01-05
申请号：US13231084
申请日：2011-09-13
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L27/06
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要翻译：半导体管芯包括具有第一和第二侧面的半导体衬底层，与半导体衬底层的第二侧相邻的金属层，在半导体衬底层的第一侧上的有源层中的一个或多个有源器件; 以及与有源层电连通的金属层中的无源器件。无源器件可以通过硅通孔（TSV）电耦合到有源层。

77. 发明授权

US08039354B2 Passive components in the back end of integrated circuits 有权
标题翻译：集成电路后端的被动元件
公开(公告)号：US08039354B2
公开(公告)日：2011-10-18
申请号：US12849086
申请日：2010-08-03
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

78. 发明授权

US07939910B2 Structure for symmetrical capacitor 有权
标题翻译：对称电容器结构
公开(公告)号：US07939910B2
公开(公告)日：2011-05-10
申请号：US12851814
申请日：2010-08-06
申请人： Choongyeun Cho , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/00
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.
摘要翻译：提供电容电路，其设置在平面前端半导体基底基板上方的下垂直电容器金属层，与底板间隔开的底板距离的平面金属底板和位于底板上方的顶板，间隔开顶板距离限定金属 - 绝缘体 - 金属电容器的基底的距离，设置在基底基板之上的顶板印迹小于底板印迹并且暴露底板剩余的上横向连接器表面; 将平行的正端口和负端口上垂直电容器金属层布置在每个顶板和底板的上部剩余侧面连接器表面上。此外，第一顶板和第二底板与正端口金属层以及第二顶板和第一底部到负极金属层的电连接赋予相等的总负端口和正端口金属 - 绝缘体 - 金属电容器外在电容。

79. 发明授权

US07853808B2 Independent processor voltage supply 有权
标题翻译：独立处理器电压供应
公开(公告)号：US07853808B2
公开(公告)日：2010-12-14
申请号：US11624333
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行或更多性能规格。标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。

80. 发明授权

US07816197B2 On-chip adjustment of MIMCAP and VNCAP capacitors 有权
标题翻译： MIMCAP和VNCAP电容器的片上调整
公开(公告)号：US07816197B2
公开(公告)日：2010-10-19
申请号：US12437575
申请日：2009-05-08
申请人： Jonghae Kim , Moon J. Kim , Jean-Oliver Plouchart , Robert E. Trzcinski
发明人： Jonghae Kim , Moon J. Kim , Jean-Oliver Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/94
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/0688 , H01L27/0808 , H01L2924/0002 , H01L2924/00
摘要： One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
摘要翻译：一个或多个片上VNCAP或MIMCAP电容器利用可变MOS电容来改善电容器的均匀电容值。这允许生产硅半导体芯片，其上安装有具有精确调节的电容值的电容器在其设计值的约1％至5％的范围内。该优化可以通过使用一对用于DC去耦的可变MOS电容器之间的背对背连接来实现。它涉及VOCAP和/或MIMCAP电容器的片上BEOL电容的并联，通过在FEOL中插入成对的背对背可变MOS电容器。

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